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[ieee754fpu.git]
/
src
/
add
/
fpcommon
/
getop.py
diff --git
a/src/add/fpcommon/getop.py
b/src/add/fpcommon/getop.py
index b966ecbd09f5861f502399a7a62c8a7a042962b6..1988997a8948abc7bad5b0c1276736c0e2fd3dc8 100644
(file)
--- a/
src/add/fpcommon/getop.py
+++ b/
src/add/fpcommon/getop.py
@@
-15,11
+15,13
@@
from multipipe import CombMuxOutPipe
from multipipe import PriorityCombMuxInPipe
from fpbase import FPState
from multipipe import PriorityCombMuxInPipe
from fpbase import FPState
+import nmoperator
class FPGetOpMod(Elaboratable):
def __init__(self, width):
self.in_op = FPOpIn(width)
class FPGetOpMod(Elaboratable):
def __init__(self, width):
self.in_op = FPOpIn(width)
+ self.in_op.data_i = Signal(width)
self.out_op = Signal(width)
self.out_decode = Signal(reset_less=True)
self.out_op = Signal(width)
self.out_decode = Signal(reset_less=True)
@@
-52,7
+54,7
@@
class FPGetOp(FPState):
""" links module to inputs and outputs
"""
setattr(m.submodules, self.state_from, self.mod)
""" links module to inputs and outputs
"""
setattr(m.submodules, self.state_from, self.mod)
- m.d.comb +=
self.mod.in_op.eq(
in_op)
+ m.d.comb +=
nmoperator.eq(self.mod.in_op,
in_op)
m.d.comb += self.out_decode.eq(self.mod.out_decode)
def action(self, m):
m.d.comb += self.out_decode.eq(self.mod.out_decode)
def action(self, m):
@@
-101,8
+103,8
@@
class FPGet2OpMod(PrevControl):
PrevControl.__init__(self)
self.width = width
self.id_wid = id_wid
PrevControl.__init__(self)
self.width = width
self.id_wid = id_wid
- self.
i_data
= self.ispec()
- self.i = self.
i_data
+ self.
data_i
= self.ispec()
+ self.i = self.
data_i
self.o = self.ospec()
def ispec(self):
self.o = self.ospec()
def ispec(self):
@@
-118,7
+120,7
@@
class FPGet2OpMod(PrevControl):
m = PrevControl.elaborate(self, platform)
with m.If(self.trigger):
m.d.comb += [
m = PrevControl.elaborate(self, platform)
with m.If(self.trigger):
m.d.comb += [
- self.o.eq(self.
i_data
),
+ self.o.eq(self.
data_i
),
]
return m
]
return m