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[ieee754fpu.git]
/
src
/
add
/
nmigen_div_experiment.py
diff --git
a/src/add/nmigen_div_experiment.py
b/src/add/nmigen_div_experiment.py
index eb0c9351614852f1eba2bb2fdc6e31e259efbd2b..a7e215cb888817b750426af676a7825552dee431 100644
(file)
--- a/
src/add/nmigen_div_experiment.py
+++ b/
src/add/nmigen_div_experiment.py
@@
-5,8
+5,8
@@
from nmigen import Module, Signal, Const, Cat
from nmigen.cli import main, verilog
from nmigen import Module, Signal, Const, Cat
from nmigen.cli import main, verilog
-from fpbase import FPNumIn, FPNumOut, FPOp
, Overflow, FPBas
e
-from
nmigen_add_experiment import FPState
+from fpbase import FPNumIn, FPNumOut, FPOp
In, FPOpOut, Overflow, FPBase, FPStat
e
+from
singlepipe import eq
class Div:
def __init__(self, width):
class Div:
def __init__(self, width):
@@
-33,9
+33,9
@@
class FPDIV(FPBase):
FPBase.__init__(self)
self.width = width
FPBase.__init__(self)
self.width = width
- self.in_a = FPOp(width)
- self.in_b = FPOp(width)
- self.out_z = FPOp(width)
+ self.in_a = FPOp
In
(width)
+ self.in_b = FPOp
In
(width)
+ self.out_z = FPOp
Out
(width)
self.states = []
self.states = []
@@
-43,7
+43,7
@@
class FPDIV(FPBase):
self.states.append(state)
return state
self.states.append(state)
return state
- def
get_fragment
(self, platform=None):
+ def
elaborate
(self, platform=None):
""" creates the HDL code-fragment for FPDiv
"""
m = Module()
""" creates the HDL code-fragment for FPDiv
"""
m = Module()
@@
-61,19
+61,24
@@
class FPDIV(FPBase):
m.submodules.z = z
m.submodules.of = of
m.submodules.z = z
m.submodules.of = of
+ m.d.comb += a.v.eq(self.in_a.v)
+ m.d.comb += b.v.eq(self.in_b.v)
+
with m.FSM() as fsm:
# ******
# gets operand a
with m.State("get_a"):
with m.FSM() as fsm:
# ******
# gets operand a
with m.State("get_a"):
- self.get_op(m, self.in_a, a, "get_b")
+ res = self.get_op(m, self.in_a, a, "get_b")
+ m.d.sync += eq([a, self.in_a.ready_o], res)
# ******
# gets operand b
with m.State("get_b"):
# ******
# gets operand b
with m.State("get_b"):
- self.get_op(m, self.in_b, b, "special_cases")
+ res = self.get_op(m, self.in_b, b, "special_cases")
+ m.d.sync += eq([b, self.in_b.ready_o], res)
# ******
# special cases: NaNs, infs, zeros, denormalised
# ******
# special cases: NaNs, infs, zeros, denormalised