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got fpdiv up and running again
[ieee754fpu.git]
/
src
/
add
/
nmigen_div_experiment.py
diff --git
a/src/add/nmigen_div_experiment.py
b/src/add/nmigen_div_experiment.py
index 918713a0bbd94d9d49a1bdd3db412df618b6ee12..ff4c966828369c9a347ee34d49c3b040840e29b8 100644
(file)
--- a/
src/add/nmigen_div_experiment.py
+++ b/
src/add/nmigen_div_experiment.py
@@
-5,7
+5,7
@@
from nmigen import Module, Signal, Const, Cat
from nmigen.cli import main, verilog
from nmigen import Module, Signal, Const, Cat
from nmigen.cli import main, verilog
-from fpbase import FPNum, FPOp, Overflow, FPBase
+from fpbase import FPNum
In, FPNumOut
, FPOp, Overflow, FPBase
class Div:
def __init__(self, width):
class Div:
def __init__(self, width):
@@
-14,7
+14,7
@@
class Div:
self.dor = Signal(width) # divisor
self.dend = Signal(width) # dividend
self.rem = Signal(width) # remainder
self.dor = Signal(width) # divisor
self.dend = Signal(width) # dividend
self.rem = Signal(width) # remainder
- self.count = Signal(
6
) # loop count
+ self.count = Signal(
7
) # loop count
self.czero = Const(0, width)
self.czero = Const(0, width)
@@
-22,7
+22,7
@@
class Div:
m.d.sync += [
self.quot.eq(self.czero),
self.rem.eq(self.czero),
m.d.sync += [
self.quot.eq(self.czero),
self.rem.eq(self.czero),
- self.count.eq(Const(0,
6
))
+ self.count.eq(Const(0,
7
))
]
]
@@
-42,13
+42,17
@@
class FPDIV(FPBase):
m = Module()
# Latches
m = Module()
# Latches
- a = FPNum
(
self.width, False)
- b = FPNum
(
self.width, False)
- z = FPNum(self.width, False)
+ a = FPNum
In(None,
self.width, False)
+ b = FPNum
In(None,
self.width, False)
+ z = FPNum
Out
(self.width, False)
- div = Div(
51)
+ div = Div(
a.m_width*2 + 3) # double the mantissa width plus g/r/sticky
of = Overflow()
of = Overflow()
+ m.submodules.in_a = a
+ m.submodules.in_b = b
+ m.submodules.z = z
+ m.submodules.of = of
with m.FSM() as fsm:
with m.FSM() as fsm:
@@
-72,42
+76,38
@@
class FPDIV(FPBase):
with m.State("special_cases"):
# if a is NaN or b is NaN return NaN
with m.State("special_cases"):
# if a is NaN or b is NaN return NaN
- with m.If(a.is_nan
() | b.is_nan()
):
+ with m.If(a.is_nan
| b.is_nan
):
m.next = "put_z"
m.d.sync += z.nan(1)
# if a is Inf and b is Inf return NaN
m.next = "put_z"
m.d.sync += z.nan(1)
# if a is Inf and b is Inf return NaN
- with m.Elif(a.is_inf
() | b.is_inf()
):
+ with m.Elif(a.is_inf
& b.is_inf
):
m.next = "put_z"
m.d.sync += z.nan(1)
# if a is inf return inf (or NaN if b is zero)
m.next = "put_z"
m.d.sync += z.nan(1)
# if a is inf return inf (or NaN if b is zero)
- with m.Elif(a.is_inf
()
):
+ with m.Elif(a.is_inf):
m.next = "put_z"
m.next = "put_z"
- # if b is zero return NaN
- with m.If(b.is_zero()):
- m.d.sync += z.nan(1)
- with m.Else():
- m.d.sync += z.inf(a.s ^ b.s)
+ m.d.sync += z.inf(a.s ^ b.s)
# if b is inf return zero
# if b is inf return zero
- with m.Elif(b.is_inf
()
):
+ with m.Elif(b.is_inf):
m.next = "put_z"
m.d.sync += z.zero(a.s ^ b.s)
m.next = "put_z"
m.d.sync += z.zero(a.s ^ b.s)
- # if a is
inf
return zero (or NaN if b is zero)
- with m.Elif(a.is_
inf()
):
+ # if a is
zero
return zero (or NaN if b is zero)
+ with m.Elif(a.is_
zero
):
m.next = "put_z"
# if b is zero return NaN
m.next = "put_z"
# if b is zero return NaN
- with m.If(b.is_zero
()
):
+ with m.If(b.is_zero):
m.d.sync += z.nan(1)
with m.Else():
m.d.sync += z.nan(1)
with m.Else():
- m.d.sync += z.
inf
(a.s ^ b.s)
+ m.d.sync += z.
zero
(a.s ^ b.s)
# if b is zero return Inf
# if b is zero return Inf
- with m.Elif(b.is_zero
()
):
+ with m.Elif(b.is_zero):
m.next = "put_z"
m.next = "put_z"
- m.d.sync += z.
zero
(a.s ^ b.s)
+ m.d.sync += z.
inf
(a.s ^ b.s)
# Denormalised Number checks
with m.Else():
# Denormalised Number checks
with m.Else():
@@
-135,7
+135,7
@@
class FPDIV(FPBase):
m.d.sync += [
z.s.eq(a.s ^ b.s), # sign
z.e.eq(a.e - b.e), # exponent
m.d.sync += [
z.s.eq(a.s ^ b.s), # sign
z.e.eq(a.e - b.e), # exponent
- div.dend.eq(a.m<<
27),
+ div.dend.eq(a.m<<
(a.m_width+3)), # 3 bits for g/r/sticky
div.dor.eq(b.m),
]
div.reset(m)
div.dor.eq(b.m),
]
div.reset(m)
@@
-147,7
+147,7
@@
class FPDIV(FPBase):
m.next = "divide_2"
m.d.sync += [
div.quot.eq(div.quot << 1),
m.next = "divide_2"
m.d.sync += [
div.quot.eq(div.quot << 1),
- div.rem.eq(Cat(div.dend[
50
], div.rem[0:])),
+ div.rem.eq(Cat(div.dend[
-1
], div.rem[0:])),
div.dend.eq(div.dend << 1),
]
div.dend.eq(div.dend << 1),
]
@@
-176,7
+176,7
@@
class FPDIV(FPBase):
with m.State("divide_3"):
m.next = "normalise_1"
m.d.sync += [
with m.State("divide_3"):
m.next = "normalise_1"
m.d.sync += [
- z.m.eq(div.quot[3:
27
]),
+ z.m.eq(div.quot[3:]),
of.guard.eq(div.quot[2]),
of.round_bit.eq(div.quot[1]),
of.sticky.eq(div.quot[0] | (div.rem != 0))
of.guard.eq(div.quot[2]),
of.round_bit.eq(div.quot[1]),
of.sticky.eq(div.quot[0] | (div.rem != 0))
@@
-198,7
+198,8
@@
class FPDIV(FPBase):
# rounding stage
with m.State("round"):
# rounding stage
with m.State("round"):
- self.roundz(m, z, of, "corrections")
+ self.roundz(m, z, of.roundz)
+ m.next = "corrections"
# ******
# correction stage
# ******
# correction stage