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got fpdiv up and running again
[ieee754fpu.git]
/
src
/
add
/
nmigen_div_experiment.py
diff --git
a/src/add/nmigen_div_experiment.py
b/src/add/nmigen_div_experiment.py
index f5adb9dbd63b9edaf81b35359b74e57d04f484f0..ff4c966828369c9a347ee34d49c3b040840e29b8 100644
(file)
--- a/
src/add/nmigen_div_experiment.py
+++ b/
src/add/nmigen_div_experiment.py
@@
-5,7
+5,7
@@
from nmigen import Module, Signal, Const, Cat
from nmigen.cli import main, verilog
from nmigen import Module, Signal, Const, Cat
from nmigen.cli import main, verilog
-from fpbase import FPNum, FPOp, Overflow, FPBase
+from fpbase import FPNum
In, FPNumOut
, FPOp, Overflow, FPBase
class Div:
def __init__(self, width):
class Div:
def __init__(self, width):
@@
-42,13
+42,17
@@
class FPDIV(FPBase):
m = Module()
# Latches
m = Module()
# Latches
- a = FPNum
(
self.width, False)
- b = FPNum
(
self.width, False)
- z = FPNum(self.width, False)
+ a = FPNum
In(None,
self.width, False)
+ b = FPNum
In(None,
self.width, False)
+ z = FPNum
Out
(self.width, False)
div = Div(a.m_width*2 + 3) # double the mantissa width plus g/r/sticky
of = Overflow()
div = Div(a.m_width*2 + 3) # double the mantissa width plus g/r/sticky
of = Overflow()
+ m.submodules.in_a = a
+ m.submodules.in_b = b
+ m.submodules.z = z
+ m.submodules.of = of
with m.FSM() as fsm:
with m.FSM() as fsm:
@@
-72,36
+76,36
@@
class FPDIV(FPBase):
with m.State("special_cases"):
# if a is NaN or b is NaN return NaN
with m.State("special_cases"):
# if a is NaN or b is NaN return NaN
- with m.If(a.is_nan
() | b.is_nan()
):
+ with m.If(a.is_nan
| b.is_nan
):
m.next = "put_z"
m.d.sync += z.nan(1)
# if a is Inf and b is Inf return NaN
m.next = "put_z"
m.d.sync += z.nan(1)
# if a is Inf and b is Inf return NaN
- with m.Elif(a.is_inf
() & b.is_inf()
):
+ with m.Elif(a.is_inf
& b.is_inf
):
m.next = "put_z"
m.d.sync += z.nan(1)
# if a is inf return inf (or NaN if b is zero)
m.next = "put_z"
m.d.sync += z.nan(1)
# if a is inf return inf (or NaN if b is zero)
- with m.Elif(a.is_inf
()
):
+ with m.Elif(a.is_inf):
m.next = "put_z"
m.d.sync += z.inf(a.s ^ b.s)
# if b is inf return zero
m.next = "put_z"
m.d.sync += z.inf(a.s ^ b.s)
# if b is inf return zero
- with m.Elif(b.is_inf
()
):
+ with m.Elif(b.is_inf):
m.next = "put_z"
m.d.sync += z.zero(a.s ^ b.s)
# if a is zero return zero (or NaN if b is zero)
m.next = "put_z"
m.d.sync += z.zero(a.s ^ b.s)
# if a is zero return zero (or NaN if b is zero)
- with m.Elif(a.is_zero
()
):
+ with m.Elif(a.is_zero):
m.next = "put_z"
# if b is zero return NaN
m.next = "put_z"
# if b is zero return NaN
- with m.If(b.is_zero
()
):
+ with m.If(b.is_zero):
m.d.sync += z.nan(1)
with m.Else():
m.d.sync += z.zero(a.s ^ b.s)
# if b is zero return Inf
m.d.sync += z.nan(1)
with m.Else():
m.d.sync += z.zero(a.s ^ b.s)
# if b is zero return Inf
- with m.Elif(b.is_zero
()
):
+ with m.Elif(b.is_zero):
m.next = "put_z"
m.d.sync += z.inf(a.s ^ b.s)
m.next = "put_z"
m.d.sync += z.inf(a.s ^ b.s)
@@
-194,7
+198,8
@@
class FPDIV(FPBase):
# rounding stage
with m.State("round"):
# rounding stage
with m.State("round"):
- self.roundz(m, z, of, "corrections")
+ self.roundz(m, z, of.roundz)
+ m.next = "corrections"
# ******
# correction stage
# ******
# correction stage