+ yield
+
+ sig123 = yield dut.sig123
+ print ("sig123", hex(sig123))
+ assert sig123 == 0x1000a0005
+
+
+
+class RecordTest2(Elaboratable):
+
+ def __init__(self):
+ self.r1 = RecordObject()
+ self.r1.sig1 = Signal(16)
+ self.r1.r2 = RecordObject()
+ self.r1.r2.sig2 = Signal(16)
+ self.r1.r3 = RecordObject()
+ self.r1.r3.sig3 = Signal(16)
+ self.sig123 = Signal(48)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ m.d.comb += cat(self.r1).eq(self.sig123)
+
+ return m
+
+
+def testbench2(dut):
+
+ sig123 = yield dut.sig123.eq(0x1000a0005)
+
+ yield
+
+ sig1 = yield dut.r1.sig1
+ assert sig1 == 5
+ sig2 = yield dut.r1.r2.sig2
+ assert sig2 == 10
+ sig3 = yield dut.r1.r3.sig3
+ assert sig3 == 1
+