-from nmigen import Module, Signal, Mux, Const
+from nmigen import Module, Signal, Mux, Const, Elaboratable
from nmigen.hdl.rec import Record
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
from nmigen.hdl.rec import Record
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
- yield dut.n.i_ready.eq(1)
- yield dut.p.i_data.eq(5)
- yield dut.p.i_valid.eq(1)
+ yield dut.n.ready_i.eq(1)
+ yield dut.p.data_i.eq(5)
+ yield dut.p.valid_i.eq(1)
yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
yield
yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
yield
yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
- yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
- yield dut.p.i_data.eq(9)
+ yield dut.n.ready_i.eq(0) # begin going into "stall" (next stage says ready)
+ yield dut.p.data_i.eq(9)
- yield dut.n.i_ready.eq(1)
- yield dut.p.i_data.eq(5)
- yield dut.p.i_valid.eq(1)
+ yield dut.n.ready_i.eq(1)
+ yield dut.p.data_i.eq(5)
+ yield dut.p.valid_i.eq(1)
yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
yield
yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
yield
yield from check_o_n_valid2(dut, 0) # effects of i_p_valid delayed 2 clocks
- yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
- yield dut.p.i_data.eq(9)
+ yield dut.n.ready_i.eq(0) # begin going into "stall" (next stage says ready)
+ yield dut.p.data_i.eq(9)
stall_range = randint(0, 3)
for j in range(randint(1,10)):
stall = randint(0, stall_range) != 0
stall_range = randint(0, 3)
for j in range(randint(1,10)):
stall = randint(0, stall_range) != 0
- o_data = yield self.dut.n.o_data
- self.resultfn(o_data, self.data[self.o], self.i, self.o)
+ data_o = yield self.dut.n.data_o
+ self.resultfn(data_o, self.data[self.o], self.i, self.o)
-def resultfn_3(o_data, expected, i, o):
- assert o_data == expected + 1, \
+def resultfn_3(data_o, expected, i, o):
+ assert data_o == expected + 1, \
- % (i, o, o_data, expected)
+ % (i, o, data_o, expected)
stall_range = randint(0, 3)
for j in range(randint(1,10)):
ready = randint(0, stall_range) != 0
stall_range = randint(0, 3)
for j in range(randint(1,10)):
ready = randint(0, stall_range) != 0
- if isinstance(self.dut.n.o_data, Record):
- o_data = {}
- dod = self.dut.n.o_data
+ if isinstance(self.dut.n.data_o, Record):
+ data_o = {}
+ dod = self.dut.n.data_o
- o_data = yield self.dut.n.o_data
- self.resultfn(o_data, self.data[self.o], self.i, self.o)
+ data_o = yield self.dut.n.data_o
+ self.resultfn(data_o, self.data[self.o], self.i, self.o)
-def resultfn_5(o_data, expected, i, o):
+def resultfn_5(data_o, expected, i, o):
- % (i, o, o_data, repr(expected))
+ % (i, o, data_o, repr(expected))
while True:
stall = randint(0, 3) != 0
send = randint(0, 5) != 0
while True:
stall = randint(0, 3) != 0
send = randint(0, 5) != 0
- o_data = yield dut.n.o_data
- assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
- % (i, o, o_data, data[o])
+ data_o = yield dut.n.data_o
+ assert data_o == data[o] + 2, "%d-%d data %x not match %x\n" \
+ % (i, o, data_o, data[o])
-def resultfn_9(o_data, expected, i, o):
+def resultfn_9(data_o, expected, i, o):
######################################################################
# Test 6 and 10
######################################################################
######################################################################
# Test 6 and 10
######################################################################
def __init__(self, width, signed):
self.m = Module()
self.src1 = Signal((width, signed), name="src1")
def __init__(self, width, signed):
self.m = Module()
self.src1 = Signal((width, signed), name="src1")
- def ispec(self):
- return (Signal(16, name="sig1"), Signal(16, "sig2"))
+ def ispec(self, name):
+ return (Signal(16, name="%s_sig1" % name),
+ Signal(16, name="%s_sig2" % name))
-def resultfn_6(o_data, expected, i, o):
+def resultfn_6(data_o, expected, i, o):
- % (i, o, o_data, repr(expected))
+ % (i, o, data_o, repr(expected))
-def resultfn_7(o_data, expected, i, o):
+def resultfn_7(data_o, expected, i, o):
- % (i, o, repr(o_data), repr(expected))
+ % (i, o, repr(data_o), repr(expected))
-def resultfn_test11(o_data, expected, i, o):
+def resultfn_test11(data_o, expected, i, o):
- % (i, o, repr(o_data), repr(expected))
+ % (i, o, repr(data_o), repr(expected))
-def resultfn_8(o_data, expected, i, o):
+def resultfn_8(data_o, expected, i, o):
- % (i, o, repr(o_data), res, repr(expected))
+ % (i, o, repr(data_o), res, repr(expected))
-def resultfn_12(o_data, expected, i, o):
+def resultfn_12(data_o, expected, i, o):
class ExampleBufModeUnBufPipe(ControlBase):
def elaborate(self, platform):
class ExampleBufModeUnBufPipe(ControlBase):
def elaborate(self, platform):
stage = PassThroughStage(self.iospecfn)
PassThroughHandshake.__init__(self, stage)
stage = PassThroughStage(self.iospecfn)
PassThroughHandshake.__init__(self, stage)
-def resultfn_identical(o_data, expected, i, o):
+def resultfn_identical(data_o, expected, i, o):
class ExampleBufPassThruPipe(ControlBase):
def elaborate(self, platform):
class ExampleBufPassThruPipe(ControlBase):
def elaborate(self, platform):
# XXX currently fails: any other permutation works fine.
# p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
# XXX currently fails: any other permutation works fine.
# p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
class ExampleFIFOPassThruPipe1(ControlBase):
def elaborate(self, platform):
class ExampleFIFOPassThruPipe1(ControlBase):
def elaborate(self, platform):
class ExampleFIFORecordObjectPipe(ControlBase):
def elaborate(self, platform):
class ExampleFIFORecordObjectPipe(ControlBase):
def elaborate(self, platform):
class ExampleFIFOAdd2Pipe(ControlBase):
def elaborate(self, platform):
class ExampleFIFOAdd2Pipe(ControlBase):
def elaborate(self, platform):
class ExampleBufPassThruPipe2(ControlBase):
def elaborate(self, platform):
class ExampleBufPassThruPipe2(ControlBase):
def elaborate(self, platform):
# XXX currently fails: any other permutation works fine.
# p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
# XXX currently fails: any other permutation works fine.
# p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
class ExampleBufUnBufPipe(ControlBase):
def elaborate(self, platform):
class ExampleBufUnBufPipe(ControlBase):
def elaborate(self, platform):
# XXX currently fails: any other permutation works fine.
# p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
# XXX currently fails: any other permutation works fine.
# p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
- print ("test 1")
- dut = ExampleBufPipe()
- run_simulation(dut, tbench(dut), vcd_name="test_bufpipe.vcd")
-
- print ("test 2")
- dut = ExampleBufPipe2()
- run_simulation(dut, tbench2(dut), vcd_name="test_bufpipe2.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
- vl = rtlil.convert(dut, ports=ports)
- with open("test_bufpipe2.il", "w") as f:
- f.write(vl)
+ if False:
+ print ("test 1")
+ dut = ExampleBufPipe()
+ run_simulation(dut, tbench(dut), vcd_name="test_bufpipe.vcd")
+
+ print ("test 2")
+ dut = ExampleBufPipe2()
+ run_simulation(dut, tbench2(dut), vcd_name="test_bufpipe2.vcd")
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_bufpipe2.il", "w") as f:
+ f.write(vl)
test = Test5(dut, resultfn_6)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
test = Test5(dut, resultfn_6)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- list(dut.p.i_data) + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ list(dut.p.data_i) + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_ltcomb_pipe.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_ltcomb_pipe.il", "w") as f:
f.write(vl)
dut = ExampleAddRecordPipe()
data=data_dict()
test = Test5(dut, resultfn_7, data=data)
dut = ExampleAddRecordPipe()
data=data_dict()
test = Test5(dut, resultfn_7, data=data)
- run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord.vcd")
-
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready,
- dut.p.i_data.src1, dut.p.i_data.src2,
- dut.n.o_data.src1, dut.n.o_data.src2]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o,
+ dut.p.data_i.src1, dut.p.data_i.src2,
+ dut.n.data_o.src1, dut.n.data_o.src2]
vl = rtlil.convert(dut, ports=ports)
with open("test_recordcomb_pipe.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_recordcomb_pipe.il", "w") as f:
f.write(vl)
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipechain2.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipechain2.il", "w") as f:
f.write(vl)
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe12.vcd")
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe12.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipe12.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipe12.il", "w") as f:
f.write(vl)
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe13.vcd")
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe13.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_unbufpipe13.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_unbufpipe13.il", "w") as f:
f.write(vl)
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf15.vcd")
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf15.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf15.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf15.il", "w") as f:
f.write(vl)
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd")
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf16.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf16.il", "w") as f:
f.write(vl)
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe17.vcd")
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe17.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_unbufpipe17.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_unbufpipe17.il", "w") as f:
f.write(vl)
data = data_chain1()
test = Test5(dut, resultfn_identical, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_passthru18.vcd")
data = data_chain1()
test = Test5(dut, resultfn_identical, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_passthru18.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_passthru18.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_passthru18.il", "w") as f:
f.write(vl)
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass19.vcd")
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass19.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpass19.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpass19.il", "w") as f:
f.write(vl)
data = data_chain1()
test = Test5(dut, resultfn_identical, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifo20.vcd")
data = data_chain1()
test = Test5(dut, resultfn_identical, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifo20.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_fifo20.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_fifo20.il", "w") as f:
f.write(vl)
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifopass21.vcd")
data = data_chain1()
test = Test5(dut, resultfn_12, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifopass21.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_fifopass21.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_fifopass21.il", "w") as f:
f.write(vl)
data=data_2op()
test = Test5(dut, resultfn_8, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord22.vcd")
data=data_2op()
test = Test5(dut, resultfn_8, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord22.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data.op1, dut.p.i_data.op2] + \
- [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i.op1, dut.p.data_i.op2] + \
+ [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_addrecord22.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_addrecord22.il", "w") as f:
f.write(vl)
data=data_2op()
test = Test5(dut, resultfn_8, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord23.vcd")
data=data_2op()
test = Test5(dut, resultfn_8, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_addrecord23.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data.op1, dut.p.i_data.op2] + \
- [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i.op1, dut.p.data_i.op2] + \
+ [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_addrecord23.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_addrecord23.il", "w") as f:
f.write(vl)
dut = FIFOTestRecordAddStageControl()
data=data_2op()
test = Test5(dut, resultfn_8, data=data)
dut = FIFOTestRecordAddStageControl()
data=data_2op()
test = Test5(dut, resultfn_8, data=data)
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data.op1, dut.p.i_data.op2] + \
- [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i.op1, dut.p.data_i.op2] + \
+ [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_addrecord24.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_addrecord24.il", "w") as f:
f.write(vl)
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_add2pipe25.vcd")
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_add2pipe25.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_add2pipe25.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_add2pipe25.il", "w") as f:
f.write(vl)
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass997.vcd")
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass997.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpass997.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpass997.il", "w") as f:
f.write(vl)
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd")
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipe14.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufpipe14.il", "w") as f:
f.write(vl)
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd")
data = data_chain1()
test = Test5(dut, resultfn_9, data=data)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd")
- ports = [dut.p.i_valid, dut.n.i_ready,
- dut.n.o_valid, dut.p.o_ready] + \
- [dut.p.i_data] + [dut.n.o_data]
+ ports = [dut.p.valid_i, dut.n.ready_i,
+ dut.n.valid_o, dut.p.ready_o] + \
+ [dut.p.data_i] + [dut.n.data_o]
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf999.il", "w") as f:
f.write(vl)
vl = rtlil.convert(dut, ports=ports)
with open("test_bufunbuf999.il", "w") as f:
f.write(vl)