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output less-than test to ilang
[ieee754fpu.git]
/
src
/
add
/
test_buf_pipe.py
diff --git
a/src/add/test_buf_pipe.py
b/src/add/test_buf_pipe.py
index 608046533c06e7e0e21290fdf64ade95a84f43a7..e32e2d322bc87cab445f677d0067376ce0c6b5aa 100644
(file)
--- a/
src/add/test_buf_pipe.py
+++ b/
src/add/test_buf_pipe.py
@@
-1,5
+1,7
@@
from nmigen import Module, Signal, Mux
from nmigen.compat.sim import run_simulation
from nmigen import Module, Signal, Mux
from nmigen.compat.sim import run_simulation
+from nmigen.cli import verilog, rtlil
+
from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
from example_buf_pipe import ExampleCombPipe, CombPipe
from example_buf_pipe import PrevControl, NextControl
from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
from example_buf_pipe import ExampleCombPipe, CombPipe
from example_buf_pipe import PrevControl, NextControl
@@
-19,24
+21,24
@@
def testbench(dut):
yield
#yield dut.i_p_rst.eq(0)
yield dut.n.i_ready.eq(1)
yield
#yield dut.i_p_rst.eq(0)
yield dut.n.i_ready.eq(1)
- yield dut.p.data.eq(5)
+ yield dut.p.
i_
data.eq(5)
yield dut.p.i_valid.eq(1)
yield
yield dut.p.i_valid.eq(1)
yield
- yield dut.p.data.eq(7)
+ yield dut.p.
i_
data.eq(7)
yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
yield
yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
yield
yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
- yield dut.p.data.eq(2)
+ yield dut.p.
i_
data.eq(2)
yield
yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
yield
yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
- yield dut.p.data.eq(9)
+ yield dut.p.
i_
data.eq(9)
yield
yield dut.p.i_valid.eq(0)
yield
yield dut.p.i_valid.eq(0)
- yield dut.p.data.eq(12)
+ yield dut.p.
i_
data.eq(12)
yield
yield
- yield dut.p.data.eq(32)
+ yield dut.p.
i_
data.eq(32)
yield dut.n.i_ready.eq(1)
yield
yield from check_o_n_valid(dut, 1) # buffer still needs to output
yield dut.n.i_ready.eq(1)
yield
yield from check_o_n_valid(dut, 1) # buffer still needs to output
@@
-55,25
+57,25
@@
def testbench2(dut):
yield
#yield dut.p.i_rst.eq(0)
yield dut.n.i_ready.eq(1)
yield
#yield dut.p.i_rst.eq(0)
yield dut.n.i_ready.eq(1)
- yield dut.p.data.eq(5)
+ yield dut.p.
i_
data.eq(5)
yield dut.p.i_valid.eq(1)
yield
yield dut.p.i_valid.eq(1)
yield
- yield dut.p.data.eq(7)
+ yield dut.p.
i_
data.eq(7)
yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed 2 clocks
yield
yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed 2 clocks
yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed 2 clocks
yield
yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed 2 clocks
- yield dut.p.data.eq(2)
+ yield dut.p.
i_
data.eq(2)
yield
yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
yield
yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
- yield dut.p.data.eq(9)
+ yield dut.p.
i_
data.eq(9)
yield
yield dut.p.i_valid.eq(0)
yield
yield dut.p.i_valid.eq(0)
- yield dut.p.data.eq(12)
+ yield dut.p.
i_
data.eq(12)
yield
yield
- yield dut.p.data.eq(32)
+ yield dut.p.
i_
data.eq(32)
yield dut.n.i_ready.eq(1)
yield
yield from check_o_n_valid(dut, 1) # buffer still needs to output
yield dut.n.i_ready.eq(1)
yield
yield from check_o_n_valid(dut, 1) # buffer still needs to output
@@
-113,7
+115,7
@@
class Test3:
continue
if send and self.i != len(self.data):
yield self.dut.p.i_valid.eq(1)
continue
if send and self.i != len(self.data):
yield self.dut.p.i_valid.eq(1)
- yield self.dut.p.data.eq(self.data[self.i])
+ yield self.dut.p.
i_
data.eq(self.data[self.i])
self.i += 1
else:
yield self.dut.p.i_valid.eq(0)
self.i += 1
else:
yield self.dut.p.i_valid.eq(0)
@@
-130,7
+132,7
@@
class Test3:
i_n_ready = yield self.dut.n.i_ready
if not o_n_valid or not i_n_ready:
continue
i_n_ready = yield self.dut.n.i_ready
if not o_n_valid or not i_n_ready:
continue
- o_data = yield self.dut.n.data
+ o_data = yield self.dut.n.
o_
data
self.resultfn(o_data, self.data[self.o], self.i, self.o)
self.o += 1
if self.o == len(self.data):
self.resultfn(o_data, self.data[self.o], self.i, self.o)
self.o += 1
if self.o == len(self.data):
@@
-183,7
+185,7
@@
class Test5:
i_n_ready = yield self.dut.n.i_ready
if not o_n_valid or not i_n_ready:
continue
i_n_ready = yield self.dut.n.i_ready
if not o_n_valid or not i_n_ready:
continue
- o_data = yield self.dut.n.data
+ o_data = yield self.dut.n.
o_
data
self.resultfn(o_data, self.data[self.o], self.i, self.o)
self.o += 1
if self.o == len(self.data):
self.resultfn(o_data, self.data[self.o], self.i, self.o)
self.o += 1
if self.o == len(self.data):
@@
-210,7
+212,7
@@
def testbench4(dut):
if o_p_ready:
if send and i != len(data):
yield dut.p.i_valid.eq(1)
if o_p_ready:
if send and i != len(data):
yield dut.p.i_valid.eq(1)
- yield dut.p.data.eq(data[i])
+ yield dut.p.
i_
data.eq(data[i])
i += 1
else:
yield dut.p.i_valid.eq(0)
i += 1
else:
yield dut.p.i_valid.eq(0)
@@
-218,7
+220,7
@@
def testbench4(dut):
o_n_valid = yield dut.n.o_valid
i_n_ready = yield dut.n.i_ready
if o_n_valid and i_n_ready:
o_n_valid = yield dut.n.o_valid
i_n_ready = yield dut.n.i_ready
if o_n_valid and i_n_ready:
- o_data = yield dut.n.data
+ o_data = yield dut.n.
o_
data
assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
% (i, o, o_data, data[o])
o += 1
assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
% (i, o, o_data, data[o])
o += 1
@@
-232,7
+234,7
@@
class ExampleBufPipe2:
v v
i_p_valid >>in pipe1 o_n_valid out>> i_p_valid >>in pipe2
o_p_ready <<out pipe1 i_n_ready <<in o_p_ready <<out pipe2
v v
i_p_valid >>in pipe1 o_n_valid out>> i_p_valid >>in pipe2
o_p_ready <<out pipe1 i_n_ready <<in o_p_ready <<out pipe2
- p_
data >>in pipe1 o_data out>> p_data
>>in pipe2
+ p_
i_data >>in pipe1 p_i_data out>> n_o_data
>>in pipe2
"""
def __init__(self):
self.pipe1 = ExampleBufPipe()
"""
def __init__(self):
self.pipe1 = ExampleBufPipe()
@@
-240,11
+242,11
@@
class ExampleBufPipe2:
# input
self.p = PrevControl()
# input
self.p = PrevControl()
- self.p.data = Signal(32) # >>in - comes in from the PREVIOUS stage
+ self.p.
i_
data = Signal(32) # >>in - comes in from the PREVIOUS stage
# output
self.n = NextControl()
# output
self.n = NextControl()
- self.n.data = Signal(32) # out>> - goes out to the NEXT stage
+ self.n.
o_
data = Signal(32) # out>> - goes out to the NEXT stage
def elaborate(self, platform):
m = Module()
def elaborate(self, platform):
m = Module()
@@
-346,3
+348,10
@@
if __name__ == '__main__':
test = Test5(dut, test6_resultfn)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
test = Test5(dut, test6_resultfn)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ list(dut.p.i_data) + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_ltcomb_pipe.il", "w") as f:
+ f.write(vl)
+