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[ieee754fpu.git]
/
src
/
add
/
test_outmux_pipe.py
diff --git
a/src/add/test_outmux_pipe.py
b/src/add/test_outmux_pipe.py
index cb91abe4dedf5ece4da588a5c5fe882655c8cc8f..b674a87069f82394ad771a5f658d8ee0838721e5 100644
(file)
--- a/
src/add/test_outmux_pipe.py
+++ b/
src/add/test_outmux_pipe.py
@@
-1,6
+1,6
@@
from random import randint
from math import log
from random import randint
from math import log
-from nmigen import Module, Signal, Cat
+from nmigen import Module, Signal, Cat
, Elaboratable
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
@@
-20,8
+20,8
@@
class PassThroughStage:
def ispec(self):
return PassInData()
def ispec(self):
return PassInData()
- def ospec(self):
- return Signal(16, name="
data_out"
, reset_less=True)
+ def ospec(self
, name
):
+ return Signal(16, name="
%s_dout" % name
, reset_less=True)
def process(self, i):
return i.data
def process(self, i):
return i.data
@@
-65,23
+65,23
@@
class OutputTest:
op2 = self.di[i][0]
mid = self.di[i][1]
rs = dut.p
op2 = self.di[i][0]
mid = self.di[i][1]
rs = dut.p
- yield rs.
i_valid
.eq(1)
- yield rs.
i_data
.data.eq(op2)
- yield rs.
i_data
.mid.eq(mid)
+ yield rs.
valid_i
.eq(1)
+ yield rs.
data_i
.data.eq(op2)
+ yield rs.
data_i
.mid.eq(mid)
yield
yield
- o_p_ready = yield rs.
o_ready
+ o_p_ready = yield rs.
ready_o
while not o_p_ready:
yield
while not o_p_ready:
yield
- o_p_ready = yield rs.
o_ready
+ o_p_ready = yield rs.
ready_o
print ("send", mid, i, hex(op2))
print ("send", mid, i, hex(op2))
- yield rs.
i_valid
.eq(0)
+ yield rs.
valid_i
.eq(0)
# wait random period of time before queueing another value
for i in range(randint(0, 3)):
yield
# wait random period of time before queueing another value
for i in range(randint(0, 3)):
yield
- yield rs.
i_valid
.eq(0)
+ yield rs.
valid_i
.eq(0)
def rcv(self, mid):
out_i = 0
def rcv(self, mid):
out_i = 0
@@
-91,14
+91,14
@@
class OutputTest:
count += 1
assert count != 2000, "timeout: too long"
n = self.dut.n[mid]
count += 1
assert count != 2000, "timeout: too long"
n = self.dut.n[mid]
- yield n.
i_ready
.eq(1)
+ yield n.
ready_i
.eq(1)
yield
yield
- o_n_valid = yield n.
o_valid
- i_n_ready = yield n.
i_ready
+ o_n_valid = yield n.
valid_o
+ i_n_ready = yield n.
ready_i
if not o_n_valid or not i_n_ready:
continue
if not o_n_valid or not i_n_ready:
continue
- out_v = yield n.
o_data
+ out_v = yield n.
data_o
print ("recv", mid, out_i, hex(out_v))
print ("recv", mid, out_i, hex(out_v))
@@
-110,7
+110,7
@@
class OutputTest:
stall_range = randint(0, 3)
stall = randint(0, stall_range) != 0
if stall:
stall_range = randint(0, 3)
stall = randint(0, stall_range) != 0
if stall:
- yield n.
i_ready
.eq(0)
+ yield n.
ready_i
.eq(0)
for i in range(stall_range):
yield
for i in range(stall_range):
yield
@@
-122,7
+122,7
@@
class TestPriorityMuxPipe(CombMuxOutPipe):
CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
-class TestSyncToPriorityPipe:
+class TestSyncToPriorityPipe
(Elaboratable)
:
def __init__(self):
self.num_rows = 4
self.pipe = PassThroughPipe()
def __init__(self):
self.num_rows = 4
self.pipe = PassThroughPipe()
@@
-139,12
+139,12
@@
class TestSyncToPriorityPipe:
return m
def ports(self):
return m
def ports(self):
- res = [self.p.
i_valid, self.p.o_ready
] + \
- self.p.
i_data
.ports()
+ res = [self.p.
valid_i, self.p.ready_o
] + \
+ self.p.
data_i
.ports()
for i in range(len(self.n)):
for i in range(len(self.n)):
- res += [self.n[i].
i_ready, self.n[i].o_valid
] + \
- [self.n[i].
o_data
]
- #self.n[i].
o_data
.ports()
+ res += [self.n[i].
ready_i, self.n[i].valid_o
] + \
+ [self.n[i].
data_o
]
+ #self.n[i].
data_o
.ports()
return res
return res