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[ieee754fpu.git]
/
src
/
add
/
test_prioritymux_pipe.py
diff --git
a/src/add/test_prioritymux_pipe.py
b/src/add/test_prioritymux_pipe.py
index 0795cccd789ce2f2091cf7bdd8b1725dc468637b..5f7891e881271fad4ba5f730d8d9070c29e38024 100644
(file)
--- a/
src/add/test_prioritymux_pipe.py
+++ b/
src/add/test_prioritymux_pipe.py
@@
-4,6
+4,7
@@
from nmigen import Module, Signal, Cat
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
+from singlepipe import PassThroughStage
from multipipe import (CombMultiInPipeline, PriorityCombMuxInPipe)
from multipipe import (CombMultiInPipeline, PriorityCombMuxInPipe)
@@
-20,16
+21,6
@@
class PassData:
return [self.mid, self.idx, self.data]
return [self.mid, self.idx, self.data]
-class PassThroughStage:
- def ispec(self):
- return PassData()
- def ospec(self):
- return self.ispec() # same as ospec
- def process(self, i):
- return i # pass-through
-
-
-
def testbench(dut):
stb = yield dut.out_op.stb
assert stb == 0
def testbench(dut):
stb = yield dut.out_op.stb
assert stb == 0
@@
-140,24
+131,24
@@
class InputTest:
for i in range(self.tlen):
op2 = self.di[mid][i]
rs = dut.p[mid]
for i in range(self.tlen):
op2 = self.di[mid][i]
rs = dut.p[mid]
- yield rs.
i_valid
.eq(1)
- yield rs.
i_data
.data.eq(op2)
- yield rs.
i_data
.idx.eq(i)
- yield rs.
i_data
.mid.eq(mid)
+ yield rs.
valid_i
.eq(1)
+ yield rs.
data_i
.data.eq(op2)
+ yield rs.
data_i
.idx.eq(i)
+ yield rs.
data_i
.mid.eq(mid)
yield
yield
- o_p_ready = yield rs.
o_ready
+ o_p_ready = yield rs.
ready_o
while not o_p_ready:
yield
while not o_p_ready:
yield
- o_p_ready = yield rs.
o_ready
+ o_p_ready = yield rs.
ready_o
print ("send", mid, i, hex(op2))
print ("send", mid, i, hex(op2))
- yield rs.
i_valid
.eq(0)
+ yield rs.
valid_i
.eq(0)
# wait random period of time before queueing another value
for i in range(randint(0, 3)):
yield
# wait random period of time before queueing another value
for i in range(randint(0, 3)):
yield
- yield rs.
i_valid
.eq(0)
+ yield rs.
valid_i
.eq(0)
## wait random period of time before queueing another value
#for i in range(randint(0, 3)):
# yield
## wait random period of time before queueing another value
#for i in range(randint(0, 3)):
# yield
@@
-173,19
+164,19
@@
class InputTest:
#stall_range = randint(0, 3)
#for j in range(randint(1,10)):
# stall = randint(0, stall_range) != 0
#stall_range = randint(0, 3)
#for j in range(randint(1,10)):
# stall = randint(0, stall_range) != 0
- # yield self.dut.n[0].
i_ready
.eq(stall)
+ # yield self.dut.n[0].
ready_i
.eq(stall)
# yield
n = self.dut.n
# yield
n = self.dut.n
- yield n.
i_ready
.eq(1)
+ yield n.
ready_i
.eq(1)
yield
yield
- o_n_valid = yield n.
o_valid
- i_n_ready = yield n.
i_ready
+ o_n_valid = yield n.
valid_o
+ i_n_ready = yield n.
ready_i
if not o_n_valid or not i_n_ready:
continue
if not o_n_valid or not i_n_ready:
continue
- mid = yield n.
o_data
.mid
- out_i = yield n.
o_data
.idx
- out_v = yield n.
o_data
.data
+ mid = yield n.
data_o
.mid
+ out_i = yield n.
data_o
.idx
+ out_v = yield n.
data_o
.data
print ("recv", mid, out_i, hex(out_v))
print ("recv", mid, out_i, hex(out_v))
@@
-207,7
+198,8
@@
class InputTest:
class TestPriorityMuxPipe(PriorityCombMuxInPipe):
def __init__(self):
self.num_rows = 4
class TestPriorityMuxPipe(PriorityCombMuxInPipe):
def __init__(self):
self.num_rows = 4
- stage = PassThroughStage()
+ def iospecfn(): return PassData()
+ stage = PassThroughStage(iospecfn)
PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)