-class InputPriorityArbiter:
- def __init__(self, pipe, num_rows):
- self.pipe = pipe
- self.num_rows = num_rows
- self.mmax = int(log(self.num_rows) / log(2))
- self.m_id = Signal(self.mmax, reset_less=True) # multiplex id
- self.active = Signal(reset_less=True)
-
- def elaborate(self, platform):
- m = Module()
-
- assert len(self.pipe.p) == self.num_rows, \
- "must declare input to be same size"
- pe = PriorityEncoder(self.num_rows)
- m.submodules.selector = pe
-
- # connect priority encoder
- in_ready = []
- for i in range(self.num_rows):
- p_i_valid = Signal(reset_less=True)
- m.d.comb += p_i_valid.eq(self.pipe.p[i].i_valid_logic())
- in_ready.append(p_i_valid)
- m.d.comb += pe.i.eq(Cat(*in_ready)) # array of input "valids"
- m.d.comb += self.active.eq(~pe.n) # encoder active (one input valid)
- m.d.comb += self.m_id.eq(pe.o) # output one active input
-
- return m
-
- def ports(self):
- return [self.m_id, self.active]
-
-
-class PriorityUnbufferedPipeline(UnbufferedPipeline):
- def __init__(self, stage, p_len=4):
- p_mux = InputPriorityArbiter(self, p_len)
- UnbufferedPipeline.__init__(self, stage, p_len=p_len, p_mux=p_mux)
-
- def ports(self):
- return self.p_mux.ports()
- #return UnbufferedPipeline.ports(self) + self.p_mux.ports()
-