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diplomacy: update to new API (#40)
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
pwm
/
PWM.scala
diff --git
a/src/main/scala/devices/pwm/PWM.scala
b/src/main/scala/devices/pwm/PWM.scala
index 14f365d80ab47c2f034ede917eab853f9fe05008..638100496dabfb564b597a335d05e57c68aef041 100644
(file)
--- a/
src/main/scala/devices/pwm/PWM.scala
+++ b/
src/main/scala/devices/pwm/PWM.scala
@@
-2,12
+2,12
@@
package sifive.blocks.devices.pwm
import Chisel._
package sifive.blocks.devices.pwm
import Chisel._
+import chisel3.experimental.MultiIOModule
import Chisel.ImplicitConversions._
import Chisel.ImplicitConversions._
-import config.Parameters
-import regmapper._
-import uncore.tilelink2._
-import util._
-
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
import sifive.blocks.util.GenericTimer
// Core PWM Functionality & Register Interface
import sifive.blocks.util.GenericTimer
// Core PWM Functionality & Register Interface
@@
-45,11
+45,11
@@
case class PWMParams(
cmpWidth: Int = 16)
trait HasPWMBundleContents extends Bundle {
cmpWidth: Int = 16)
trait HasPWMBundleContents extends Bundle {
-
val
params: PWMParams
+
def
params: PWMParams
val gpio = Vec(params.ncmp, Bool()).asOutput
}
val gpio = Vec(params.ncmp, Bool()).asOutput
}
-trait HasPWMModuleContents extends Module with HasRegMap {
+trait HasPWMModuleContents extends M
ultiIOM
odule with HasRegMap {
val io: HasPWMBundleContents
val params: PWMParams
val io: HasPWMBundleContents
val params: PWMParams