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Remove pluralization on interface names. Require clocks and resets explicitly when...
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
pwm
/
PWMPeriphery.scala
diff --git
a/src/main/scala/devices/pwm/PWMPeriphery.scala
b/src/main/scala/devices/pwm/PWMPeriphery.scala
index 63bbfabccc48a6f7e0a9dd256193a0fe378a93fe..31ad5f6f3a999dc32de46efc8b6149ce4beb7429 100644
(file)
--- a/
src/main/scala/devices/pwm/PWMPeriphery.scala
+++ b/
src/main/scala/devices/pwm/PWMPeriphery.scala
@@
-38,15
+38,15
@@
trait HasPeripheryPWM extends HasSystemNetworks {
}
trait HasPeripheryPWMBundle {
}
trait HasPeripheryPWMBundle {
- val pwm
s
: HeterogeneousBag[PWMPortIO]
+ val pwm: HeterogeneousBag[PWMPortIO]
}
trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
val outer: HasPeripheryPWM
}
trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
val outer: HasPeripheryPWM
- val pwm
s
= IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
+ val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
- (pwm
s
zip outer.pwms) foreach { case (io, device) =>
+ (pwm zip outer.pwms) foreach { case (io, device) =>
io.port := device.module.io.gpio
}
}
io.port := device.module.io.gpio
}
}