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"Fix" false combinational loop through SPIArbiter
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
spi
/
SPIArbiter.scala
diff --git
a/src/main/scala/devices/spi/SPIArbiter.scala
b/src/main/scala/devices/spi/SPIArbiter.scala
index b47cea3a4ba39e673056fa623617a054c12aa4a8..df87d9586cafd5c155463bd569eb166cdc623695 100644
(file)
--- a/
src/main/scala/devices/spi/SPIArbiter.scala
+++ b/
src/main/scala/devices/spi/SPIArbiter.scala
@@
-3,11
+3,11
@@
package sifive.blocks.devices.spi
import Chisel._
import Chisel._
-class SPIInnerIO(c: SPI
Config
Base) extends SPILinkIO(c) {
+class SPIInnerIO(c: SPI
Params
Base) extends SPILinkIO(c) {
val lock = Bool(OUTPUT)
}
val lock = Bool(OUTPUT)
}
-class SPIArbiter(c: SPI
Config
Base, n: Int) extends Module {
+class SPIArbiter(c: SPI
Params
Base, n: Int) extends Module {
val io = new Bundle {
val inner = Vec(n, new SPIInnerIO(c)).flip
val outer = new SPILinkIO(c)
val io = new Bundle {
val inner = Vec(n, new SPIInnerIO(c)).flip
val outer = new SPILinkIO(c)
@@
-20,7
+20,9
@@
class SPIArbiter(c: SPIConfigBase, n: Int) extends Module {
io.outer.tx.bits := Mux1H(sel, io.inner.map(_.tx.bits))
io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt))
io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt))
io.outer.tx.bits := Mux1H(sel, io.inner.map(_.tx.bits))
io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt))
io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt))
- io.outer.cs := Mux1H(sel, io.inner.map(_.cs))
+ // Workaround for overzealous combinational loop detection
+ io.outer.cs := Mux(sel(1), io.inner(0).cs, io.inner(1).cs)
+ require(n == 2, "SPIArbiter currently only supports 2 clients")
(io.inner zip sel).foreach { case (inner, s) =>
inner.tx.ready := io.outer.tx.ready && s
(io.inner zip sel).foreach { case (inner, s) =>
inner.tx.ready := io.outer.tx.ready && s