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spi: work around ucb-bar/chisel3#472
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
spi
/
SPIConsts.scala
diff --git
a/src/main/scala/devices/spi/SPIConsts.scala
b/src/main/scala/devices/spi/SPIConsts.scala
index b18b08a4acbaaed701253505d97fda22c8d1fb69..5d6dd0d15c0e4a0e24d1f2f2bfa9d4539ce2be09 100644
(file)
--- a/
src/main/scala/devices/spi/SPIConsts.scala
+++ b/
src/main/scala/devices/spi/SPIConsts.scala
@@
-5,29
+5,29
@@
import Chisel._
object SPIProtocol {
val width = 2
object SPIProtocol {
val width = 2
-
val
Single = UInt(0, width)
-
val
Dual = UInt(1, width)
-
val
Quad = UInt(2, width)
+
def
Single = UInt(0, width)
+
def
Dual = UInt(1, width)
+
def
Quad = UInt(2, width)
-
val
cases = Seq(Single, Dual, Quad)
+
def
cases = Seq(Single, Dual, Quad)
def decode(x: UInt): Seq[Bool] = cases.map(_ === x)
}
object SPIDirection {
val width = 1
def decode(x: UInt): Seq[Bool] = cases.map(_ === x)
}
object SPIDirection {
val width = 1
-
val
Rx = UInt(0, width)
-
val
Tx = UInt(1, width)
+
def
Rx = UInt(0, width)
+
def
Tx = UInt(1, width)
}
object SPIEndian {
val width = 1
}
object SPIEndian {
val width = 1
-
val
MSB = UInt(0, width)
-
val
LSB = UInt(1, width)
+
def
MSB = UInt(0, width)
+
def
LSB = UInt(1, width)
}
object SPICSMode {
val width = 2
}
object SPICSMode {
val width = 2
-
val
Auto = UInt(0, width)
-
val
Hold = UInt(2, width)
-
val
Off = UInt(3, width)
+
def
Auto = UInt(0, width)
+
def
Hold = UInt(2, width)
+
def
Off = UInt(3, width)
}
}