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diplomacy: update to new API (#40)
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
spi
/
SPIPeriphery.scala
diff --git
a/src/main/scala/devices/spi/SPIPeriphery.scala
b/src/main/scala/devices/spi/SPIPeriphery.scala
index 80978946103eec972449e71d82227beceb2b3e86..b2edb0f64f14d2f9009af8d34cfbc56d6992a953 100644
(file)
--- a/
src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/
src/main/scala/devices/spi/SPIPeriphery.scala
@@
-4,8
+4,8
@@
package sifive.blocks.devices.spi
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
-import freechips.rocketchip.diplomacy.{LazyModule,LazyM
ultiIOModuleImp
}
-import freechips.rocketchip.tilelink.{TLFragmenter}
+import freechips.rocketchip.diplomacy.{LazyModule,LazyM
oduleImp,BufferParams
}
+import freechips.rocketchip.tilelink.{TLFragmenter
,TLBuffer
}
import freechips.rocketchip.util.HeterogeneousBag
case object PeripherySPIKey extends Field[Seq[SPIParams]]
import freechips.rocketchip.util.HeterogeneousBag
case object PeripherySPIKey extends Field[Seq[SPIParams]]
@@
-25,7
+25,7
@@
trait HasPeripherySPIBundle {
}
}
-trait HasPeripherySPIModuleImp extends LazyM
ultiIOM
oduleImp with HasPeripherySPIBundle {
+trait HasPeripherySPIModuleImp extends LazyModuleImp with HasPeripherySPIBundle {
val outer: HasPeripherySPI
val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
val outer: HasPeripherySPI
val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
@@
-41,7
+41,10
@@
trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
val qspis = spiFlashParams map { params =>
val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
qspi.rnode := pbus.toVariableWidthSlaves
val qspis = spiFlashParams map { params =>
val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
qspi.rnode := pbus.toVariableWidthSlaves
- qspi.fnode := TLFragmenter(1, pbus.blockBytes)(pbus.toFixedWidthSlaves)
+ qspi.fnode :=
+ TLFragmenter(1, pbus.blockBytes)(
+ TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)(
+ pbus.toFixedWidthSlaves))
ibus.fromSync := qspi.intnode
qspi
}
ibus.fromSync := qspi.intnode
qspi
}
@@
-52,7
+55,7
@@
trait HasPeripherySPIFlashBundle {
}
}
-trait HasPeripherySPIFlashModuleImp extends LazyM
ultiIOM
oduleImp with HasPeripherySPIFlashBundle {
+trait HasPeripherySPIFlashModuleImp extends LazyModuleImp with HasPeripherySPIFlashBundle {
val outer: HasPeripherySPIFlash
val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
val outer: HasPeripherySPIFlash
val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))