-import diplomacy.LazyModule
-import uncore.tilelink2._
-import rocketchip.{TopNetwork,TopNetworkModule}
-
-trait PeripherySPI {
- this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
- val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
- val spi = LazyModule(new TLSPI(c))
- spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget}
+import freechips.rocketchip.util.HeterogeneousBag
+
+case object PeripherySPIKey extends Field[Seq[SPIParams]]
+
+trait HasPeripherySPI extends HasSystemNetworks {
+ val spiParams = p(PeripherySPIKey)
+ val spis = spiParams map { params =>
+ val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
+ spi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)