projects
/
sifive-blocks.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
spi: Fix io.port.dq(3) output enable
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
spi
/
SPIPhysical.scala
diff --git
a/src/main/scala/devices/spi/SPIPhysical.scala
b/src/main/scala/devices/spi/SPIPhysical.scala
index cb26bc99046e3dbeb273b376e397b31c611b5567..a9ce0760ce30a793c29522d47d99d4a3db4811b6 100644
(file)
--- a/
src/main/scala/devices/spi/SPIPhysical.scala
+++ b/
src/main/scala/devices/spi/SPIPhysical.scala
@@
-4,7
+4,7
@@
package sifive.blocks.devices.spi
import Chisel._
import sifive.blocks.util.ShiftRegisterInit
import Chisel._
import sifive.blocks.util.ShiftRegisterInit
-class SPIMicroOp(c: SPI
Config
Base) extends SPIBundle(c) {
+class SPIMicroOp(c: SPI
Params
Base) extends SPIBundle(c) {
val fn = Bits(width = 1)
val stb = Bool()
val cnt = UInt(width = c.countBits)
val fn = Bits(width = 1)
val stb = Bool()
val cnt = UInt(width = c.countBits)
@@
-16,12
+16,12
@@
object SPIMicroOp {
def Delay = UInt(1, 1)
}
def Delay = UInt(1, 1)
}
-class SPIPhyControl(c: SPI
Config
Base) extends SPIBundle(c) {
+class SPIPhyControl(c: SPI
Params
Base) extends SPIBundle(c) {
val sck = new SPIClocking(c)
val fmt = new SPIFormat(c)
}
val sck = new SPIClocking(c)
val fmt = new SPIFormat(c)
}
-class SPIPhysical(c: SPI
Config
Base) extends Module {
+class SPIPhysical(c: SPI
Params
Base) extends Module {
val io = new SPIBundle(c) {
val port = new SPIPortIO(c)
val ctrl = new SPIPhyControl(c).asInput
val io = new SPIBundle(c) {
val port = new SPIPortIO(c)
val ctrl = new SPIPhyControl(c).asInput
@@
-82,7
+82,7
@@
class SPIPhysical(c: SPIConfigBase) extends Module {
}
val tx = (ctrl.fmt.iodir === SPIDirection.Tx)
}
val tx = (ctrl.fmt.iodir === SPIDirection.Tx)
- val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _)
+ val txen_in = (proto.head +: proto.tail.map(_ && tx)).scanRight(Bool(false))(_ || _)
.init
val txen = txen_in :+ txen_in.last
io.port.sck := sck
val txen = txen_in :+ txen_in.last
io.port.sck := sck