projects
/
sifive-blocks.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
diplomacy: update to new API (#40)
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
uart
/
UART.scala
diff --git
a/src/main/scala/devices/uart/UART.scala
b/src/main/scala/devices/uart/UART.scala
index de2cf554a33c1a4d061317b5f182619cee25fe98..449f897819a57427a8a8e978569df70745bebe2b 100644
(file)
--- a/
src/main/scala/devices/uart/UART.scala
+++ b/
src/main/scala/devices/uart/UART.scala
@@
-2,6
+2,7
@@
package sifive.blocks.devices.uart
import Chisel._
package sifive.blocks.devices.uart
import Chisel._
+import chisel3.experimental.MultiIOModule
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
@@
-198,7
+199,7
@@
class UARTInterrupts extends Bundle {
val txwm = Bool()
}
val txwm = Bool()
}
-trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasRegMap {
+trait HasUARTTopModuleContents extends M
ultiIOM
odule with HasUARTParameters with HasRegMap {
val io: HasUARTTopBundleContents
implicit val p: Parameters
def params: UARTParams
val io: HasUARTTopBundleContents
implicit val p: Parameters
def params: UARTParams