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devices: include DTS meta-data
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
uart
/
UART.scala
diff --git
a/src/main/scala/devices/uart/UART.scala
b/src/main/scala/devices/uart/UART.scala
index 0dce16d4c60feb4c56d8b533124373d44cc8d7c9..9b3dfaa37110cb6bdd7c93f7baf99fbda52908c8 100644
(file)
--- a/
src/main/scala/devices/uart/UART.scala
+++ b/
src/main/scala/devices/uart/UART.scala
@@
-260,6
+260,6
@@
trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
// Magic TL2 Incantation to create a TL2 UART
class TLUART(w: Int, c: UARTParams)(implicit p: Parameters)
// Magic TL2 Incantation to create a TL2 UART
class TLUART(w: Int, c: UARTParams)(implicit p: Parameters)
- extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = w)(
+ extends TLRegisterRouter(c.address,
"serial", Seq("sifive,uart0"),
interrupts = 1, beatBytes = w)(
new TLRegBundle(c, _) with HasUARTTopBundleContents)(
new TLRegModule(c, _, _) with HasUARTTopModuleContents)
new TLRegBundle(c, _) with HasUARTTopBundleContents)(
new TLRegModule(c, _, _) with HasUARTTopModuleContents)