-import config.Field
-import diplomacy.LazyModule
-import rocketchip.{
- HasTopLevelNetworks,
- HasTopLevelNetworksBundle,
- HasTopLevelNetworksModule
-}
-import uncore.tilelink2._
-
-import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
-import sifive.blocks.util.ShiftRegisterInit
+import chisel3.experimental.{withClockAndReset}
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusKey, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}