-class UARTGPIOPort(syncStages: Int = 0) extends Module {
- val io = new Bundle{
- val uart = new UARTPortIO().flip()
- val pins = new UARTPinsIO
+ def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
+ withClockAndReset(clock, reset) {
+ txd.outputPin(uart.txd)
+ val rxd_t = rxd.inputPin()
+ uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
+ }