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uart: make it easy to simulate large text printouts (#33)
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
xilinxvc707mig
/
XilinxVC707MIG.scala
diff --git
a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index c248f6c5553b05f317aee6bbd285bc81c7719e9f..afaff337e3d67a340ae1b245e5f948ebd12f65a2 100644
(file)
--- a/
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@
-3,11
+3,11
@@
package sifive.blocks.devices.xilinxvc707mig
import Chisel._
import chisel3.experimental.{Analog,attach}
import Chisel._
import chisel3.experimental.{Analog,attach}
-import
config
._
-import
diplomacy._
-import
uncore.tilelink2
._
-import
uncore.axi4
._
-import
rocketchip
._
+import
freechips.rocketchip.amba.axi4
._
+import
freechips.rocketchip.config.Parameters
+import
freechips.rocketchip.coreplex
._
+import
freechips.rocketchip.diplomacy
._
+import
freechips.rocketchip.tilelink
._
import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
trait HasXilinxVC707MIGParameters {
import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
trait HasXilinxVC707MIGParameters {
@@
-32,14
+32,16
@@
class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
beatBytes = 8)))
val xing = LazyModule(new TLAsyncCrossing)
beatBytes = 8)))
val xing = LazyModule(new TLAsyncCrossing)
- val toaxi4 = LazyModule(new TLToAXI4(beatBytes = 8))
+ val toaxi4 = LazyModule(new TLToAXI4(beatBytes = 8
, adapterName = Some("mem"), stripBits = 1
))
val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
- val deint = LazyModule(new AXI4Deinterleaver(p(
coreplex.
CacheBlockBytes)))
+ val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
val yank = LazyModule(new AXI4UserYanker)
val yank = LazyModule(new AXI4UserYanker)
+ val buffer = LazyModule(new AXI4Buffer)
xing.node := node
val monitor = (toaxi4.node := xing.node)
xing.node := node
val monitor = (toaxi4.node := xing.node)
- axi4 := yank.node
+ axi4 := buffer.node
+ buffer.node := yank.node
yank.node := deint.node
deint.node := indexer.node
indexer.node := toaxi4.node
yank.node := deint.node
deint.node := indexer.node
indexer.node := toaxi4.node
@@
-75,9
+77,8
@@
class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
io.port.ddr3_odt := blackbox.io.ddr3_odt
//inputs
io.port.ddr3_odt := blackbox.io.ddr3_odt
//inputs
- //differential system clock
- blackbox.io.sys_clk_n := io.port.sys_clk_n
- blackbox.io.sys_clk_p := io.port.sys_clk_p
+ //NO_BUFFER clock
+ blackbox.io.sys_clk_i := io.port.sys_clk_i
//user interface signals
val axi_async = axi4.bundleIn(0)
//user interface signals
val axi_async = axi4.bundleIn(0)
@@
-85,7
+86,7
@@
class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
xing.module.io.in_reset := reset
xing.module.io.out_clock := blackbox.io.ui_clk
xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
xing.module.io.in_reset := reset
xing.module.io.out_clock := blackbox.io.ui_clk
xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
- (Seq(toaxi4, indexer, deint, yank) ++ monitor) foreach { lm =>
+ (Seq(toaxi4, indexer, deint, yank
, buffer
) ++ monitor) foreach { lm =>
lm.module.clock := blackbox.io.ui_clk
lm.module.reset := blackbox.io.ui_clk_sync_rst
}
lm.module.clock := blackbox.io.ui_clk
lm.module.reset := blackbox.io.ui_clk_sync_rst
}