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uart: make it easy to simulate large text printouts (#33)
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
xilinxvc707pciex1
/
XilinxVC707PCIeX1.scala
diff --git
a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
index 2e376d0fc9d7a0db3cf499ee1586a253a48dbf8b..cf8eae744e9408fa46fee00ce7cbb5a37fc5384d 100644
(file)
--- a/
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+++ b/
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
@@
-2,11
+2,11
@@
package sifive.blocks.devices.xilinxvc707pciex1
import Chisel._
package sifive.blocks.devices.xilinxvc707pciex1
import Chisel._
-import
config
._
-import
diplomacy._
-import
uncore.tilelink2._
-import
uncore.axi4
._
-import
rocketchip
._
+import
freechips.rocketchip.amba.axi4
._
+import
freechips.rocketchip.coreplex.CacheBlockBytes
+import
freechips.rocketchip.config.Parameters
+import
freechips.rocketchip.diplomacy
._
+import
freechips.rocketchip.tilelink
._
import sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
import sifive.blocks.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
import sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
import sifive.blocks.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
@@
-20,9
+20,9
@@
class XilinxVC707PCIeX1IO extends Bundle with VC707AXIToPCIeX1IOSerial
}
class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
}
class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
- val slave = TLInputNode()
- val control = TLInputNode()
- val master = TLOutputNode()
+ val slave = TL
Async
InputNode()
+ val control = TL
Async
InputNode()
+ val master = TL
Async
OutputNode()
val intnode = IntOutputNode()
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
val intnode = IntOutputNode()
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
@@
-30,25
+30,26
@@
class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
axi_to_pcie_x1.slave :=
AXI4Buffer()(
AXI4UserYanker()(
axi_to_pcie_x1.slave :=
AXI4Buffer()(
AXI4UserYanker()(
- AXI4Deinterleaver(p(
coreplex.
CacheBlockBytes))(
+ AXI4Deinterleaver(p(CacheBlockBytes))(
AXI4IdIndexer(idBits=4)(
AXI4IdIndexer(idBits=4)(
- TLToAXI4(beatBytes=8)(
- slave)))))
+ TLToAXI4(beatBytes=8, adapterName = Some("pcie-slave"))(
+ TLAsyncCrossingSink()(
+ slave))))))
axi_to_pcie_x1.control :=
AXI4Buffer()(
axi_to_pcie_x1.control :=
AXI4Buffer()(
- AXI4UserYanker()(
- AXI4Fragmenter()(
- AXI4IdIndexer(idBits=0)(
+ AXI4UserYanker(capMaxFlight = Some(2))(
TLToAXI4(beatBytes=4)(
TLToAXI4(beatBytes=4)(
+ TLFragmenter(4, p(CacheBlockBytes))(
+ TLAsyncCrossingSink()(
control)))))
master :=
control)))))
master :=
+ TLAsyncCrossingSource()(
TLWidthWidget(8)(
AXI4ToTL()(
AXI4UserYanker(capMaxFlight=Some(8))(
AXI4Fragmenter()(
TLWidthWidget(8)(
AXI4ToTL()(
AXI4UserYanker(capMaxFlight=Some(8))(
AXI4Fragmenter()(
- AXI4IdIndexer(idBits=0)(
axi_to_pcie_x1.master)))))
intnode := axi_to_pcie_x1.intnode
axi_to_pcie_x1.master)))))
intnode := axi_to_pcie_x1.intnode