+""" jk latch
+
+module jk(q,q1,j,k,c);
+output q,q1;
+input j,k,c;
+reg q,q1;
+initial begin q=1'b0; q1=1'b1; end
+always @ (posedge c)
+ begin
+ case({j,k})
+ {1'b0,1'b0}:begin q=q; q1=q1; end
+ {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
+ {1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
+ {1'b1,1'b1}: begin q=~q; q1=~q1; end
+ endcase
+ end
+endmodule
+"""
+
+def latchregister(m, incoming, outgoing, settrue):
+ reg = Signal.like(incoming) # make register same as input. reset is OK.
+ with m.If(settrue):
+ m.d.sync += reg.eq(incoming) # latch input into register
+ m.d.comb += outgoing.eq(incoming) # return input (combinatorial)
+ with m.Else():
+ m.d.comb += outgoing.eq(reg) # return input (combinatorial)
+