+class DepCell(Elaboratable):
+ """ implements 11.4.7 mitch alsup dependence cell, p27
+ adjusted to be clock-sync'd on rising edge only.
+ mitch design (as does 6600) requires alternating rising/falling clock
+ """
+ def __init__(self):
+ # inputs
+ self.reg_i = Signal(reset_less=True) # reg bit in (top)
+ self.issue_i = Signal(reset_less=True) # Issue in (top)
+ self.go_i = Signal(reset_less=True) # Go read/write in (left)
+
+ # for Register File Select Lines (vertical)
+ self.rsel_o = Signal(reset_less=True) # reg sel (bottom)
+ # for Function Unit "forward progress" (horizontal)
+ self.fwd_o = Signal(reset_less=True) # FU forard progress (right)
+
+ def elaborate(self, platform):
+ m = Module()
+ m.submodules.l = l = SRLatch(sync=False) # async latch
+
+ # record current version of q in a sync'd register
+ cq = Signal() # resets to 0
+ m.d.sync += cq.eq(l.q)
+
+ # reset on go HI, set on dest and issue
+ m.d.comb += l.s.eq(self.issue_i & self.reg_i)
+ m.d.comb += l.r.eq(self.go_i)
+
+ # Function Unit "Forward Progress".
+ m.d.comb += self.fwd_o.eq((cq | l.q) & self.reg_i & ~self.issue_i)
+
+ # Register Select. Activated on go read/write and *current* latch set
+ m.d.comb += self.rsel_o.eq((cq | l.q) & self.go_i)
+
+ return m
+
+ def __iter__(self):
+ yield self.regt_i
+ yield self.issue_i
+ yield self.go_i
+ yield self.rsel_o
+ yield self.fwd_o
+
+ def ports(self):
+ return list(self)
+
+