+
+ def ports(self):
+ return list(self)
+
+
+class DependencyRow(Elaboratable):
+ def __init__(self, n_reg_col):
+ self.n_reg_col = n_reg_col
+
+ # ----
+ # fields all match DependencyCell precisely
+
+ self.dest_i = Signal(n_reg_col, reset_less=True)
+ self.src1_i = Signal(n_reg_col, reset_less=True)
+ self.src2_i = Signal(n_reg_col, reset_less=True)
+
+ self.issue_i = Signal(reset_less=True)
+ self.go_wr_i = Signal(reset_less=True)
+ self.go_rd_i = Signal(reset_less=True)
+
+ self.dest_rsel_o = Signal(n_reg_col, reset_less=True)
+ self.src1_rsel_o = Signal(n_reg_col, reset_less=True)
+ self.src2_rsel_o = Signal(n_reg_col, reset_less=True)
+
+ self.dest_fwd_o = Signal(n_reg_col, reset_less=True)
+ self.src1_fwd_o = Signal(n_reg_col, reset_less=True)
+ self.src2_fwd_o = Signal(n_reg_col, reset_less=True)
+
+ def elaborate(self, platform):
+ m = Module()
+ rcell = Array(DependenceCell() for f in range(self.n_reg_col))
+ for rn in range(self.n_reg_col):
+ setattr(m.submodules, "dm_r%d" % rn, rcell[rn])
+
+ # ---
+ # connect Dep dest/src to module dest/src
+ # ---
+ dest_i = []
+ src1_i = []
+ src2_i = []
+ for rn in range(self.n_reg_col):
+ dc = rcell[rn]
+ # accumulate cell inputs dest/src1/src2
+ dest_i.append(dc.dest_i)
+ src1_i.append(dc.src1_i)
+ src2_i.append(dc.src2_i)
+ # wire up inputs from module to row cell inputs (Cat is gooood)
+ m.d.comb += [Cat(*dest_i).eq(self.dest_i),
+ Cat(*src1_i).eq(self.src1_i),
+ Cat(*src2_i).eq(self.src2_i),
+ ]
+
+ # ---
+ # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
+ # ---
+ for rn in range(self.n_reg_col):
+ dc = rcell[rn]
+ m.d.comb += [dc.go_rd_i.eq(self.go_rd_i),
+ dc.go_wr_i.eq(self.go_wr_i),
+ dc.issue_i.eq(self.issue_i),
+ ]
+
+ # ---
+ # connect Function Unit vector
+ # ---
+ dest_fwd_o = []
+ src1_fwd_o = []
+ src2_fwd_o = []
+ for rn in range(self.n_reg_col):
+ dc = rcell[rn]
+ # accumulate cell fwd outputs for dest/src1/src2
+ dest_fwd_o.append(dc.dest_fwd_o)
+ src1_fwd_o.append(dc.src1_fwd_o)
+ src2_fwd_o.append(dc.src2_fwd_o)
+ # connect cell fwd outputs to FU Vector Out [Cat is gooood]
+ m.d.comb += [self.dest_fwd_o.eq(Cat(*dest_fwd_o)),
+ self.src1_fwd_o.eq(Cat(*src1_fwd_o)),
+ self.src2_fwd_o.eq(Cat(*src2_fwd_o))
+ ]
+
+ # ---
+ # connect Reg Selection vector
+ # ---
+ dest_rsel_o = []
+ src1_rsel_o = []
+ src2_rsel_o = []
+ for rn in range(self.n_reg_col):
+ dc = rcell[rn]
+ # accumulate cell reg-select outputs dest/src1/src2
+ dest_rsel_o.append(dc.dest_rsel_o)
+ src1_rsel_o.append(dc.src1_rsel_o)
+ src2_rsel_o.append(dc.src2_rsel_o)
+ # connect cell reg-select outputs to Reg Vector Out
+ m.d.comb += self.dest_rsel_o.eq(Cat(*dest_rsel_o))
+ m.d.comb += self.src1_rsel_o.eq(Cat(*src1_rsel_o))
+ m.d.comb += self.src2_rsel_o.eq(Cat(*src2_rsel_o))
+
+ return m
+
+ def __iter__(self):
+ yield self.dest_i
+ yield self.src1_i
+ yield self.src2_i
+ yield self.issue_i
+ yield self.go_wr_i
+ yield self.go_rd_i
+ yield self.dest_rsel_o
+ yield self.src1_rsel_o
+ yield self.src2_rsel_o
+ yield self.dest_fwd_o
+ yield self.src1_fwd_o
+ yield self.src2_fwd_o
+