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clear out DEC in core.cur_state.dec due to spurious interrupt.
[soc.git]
/
src
/
soc
/
fu
/
spr
/
main_stage.py
diff --git
a/src/soc/fu/spr/main_stage.py
b/src/soc/fu/spr/main_stage.py
index 3e236a28bf321d050e0e140fd09551c14cfff68a..b3a49cb642e9509732eaa3763599180b718a41f9 100644
(file)
--- a/
src/soc/fu/spr/main_stage.py
+++ b/
src/soc/fu/spr/main_stage.py
@@
-56,7
+56,8
@@
class SPRMainStage(PipeModBase):
#### MTSPR ####
with m.Case(MicrOp.OP_MTSPR):
with m.Switch(spr):
#### MTSPR ####
with m.Case(MicrOp.OP_MTSPR):
with m.Switch(spr):
- # State SPRs first
+ # State SPRs first, note that this triggers a regfile write
+ # which is monitored right the way down in TestIssuerBase.
with m.Case(SPR.DEC, SPR.TB):
comb += state1_o.data.eq(a_i)
comb += state1_o.ok.eq(1)
with m.Case(SPR.DEC, SPR.TB):
comb += state1_o.data.eq(a_i)
comb += state1_o.ok.eq(1)