+The other way in which out-of-order execution can be handled is called
+scoreboarding, as well as explicit register renaming. These schemes
+seem to have significant disadvantages and complexities when compared
+to Reorder Buffers:
+
+* Explicit Register renaming needs a global register file quite a bit larger
+ than the "actual" one. The Libre RISC-V SoC already has two whopping
+ great 128-entry 64-bit register files.
+* In-order scoreboarding actually *delays* instruction execution (all of it)
+ until such time as the source registers and all other dependencies are
+ ready. The idea seems to be that the register renaming "should have taken
+ care of" as many of these dependencies as possible, in advance.
+* Unlike Tomasulo with Reorder buffers, there does not appear to be
+ any assistance in dealing with memory LOAD/STOREs.
+* There's no clear way to handle branch prediction, where the Reorder
+ Buffer of Tomasulo handles it really cleanly.
+
+Whilst nothing's firmly set in stone, here, as we have a Charter that
+requires unanimous decision-making from contributors, so far it's leaning
+towards Reorder Buffers and Tomasulo as a good, clean fit. In part that
+is down to more research having been done on that particular algorithm.
+More as it happens...
+