disallow adding verilog files

[soc-cocotb-sim.git] / .gitignore

diff --git a/.gitignore b/.gitignore
index 3a8cbad6cbf74cf7a28603724255c90a1bb4a944..ff14265ba4ba023fd82e2a19b691e66895a3b3cf 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -2,3 +2,4 @@
 __pycache__/
 sim_build_*/
 results_*.xml
+*.v