List of major changes and improvements between releases
=======================================================
-Yosys 0.14 .. Yosys 0.14-dev
+Yosys 0.17 .. Yosys 0.17-dev
--------------------------
+Yosys 0.16 .. Yosys 0.17
+--------------------------
+ * New commands and options
+ - Added "write_jny" ( JSON netlist metadata format )
+ - Added "tribuf -formal"
+
+ * SystemVerilog
+ - Fixed automatic `nosync` inference for local variables in `always_comb`
+ procedures not applying to nested blocks and blocks in functions
+
+Yosys 0.15 .. Yosys 0.16
+--------------------------
+ * Various
+ - Added BTOR2 witness file co-simulation.
+ - Simulation calls external vcd2fst for VCD conversion.
+ - Added fst2tb pass - generates testbench for the circuit using
+ the given top-level module and simulus signal from FST file.
+ - yosys-smtbmc: Option to keep going after failed assertions in BMC mode
+
+ * Verific support
+ - Import modules in alphabetic (reproducable) order.
+
+Yosys 0.14 .. Yosys 0.15
+--------------------------
+
+ * Various
+ - clk2fflogic: nice names for autogenerated signals
+ - simulation include support for all flip-flop types.
+ - Added AIGER witness file co-simulation.
+
+ * Verilog
+ - Fixed evaluation of constant functions with variables or arguments with
+ reversed dimensions
+ - Fixed elaboration of dynamic range assignments where the vector is
+ reversed or is not zero-indexed
+ - Added frontend support for time scale delay values (e.g., `#1ns`)
+
+ * SystemVerilog
+ - Added support for accessing whole sub-structures in expressions
+
+ * New commands and options
+ - Added glift command, used to create gate-level information flow tracking
+ (GLIFT) models by the "constructive mapping" approach
+
+ * Verific support
+ - Ability to override default parser mode for verific -f command.
+
Yosys 0.13 .. Yosys 0.14
--------------------------
projects / yosys.git / blobdiff