Merge pull request #3310 from robinsonb5-PRs/master

[yosys.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index d6d2c49900f5e86ac2c16e43a89bb07676058b7b..4004c534b8e1e75e330f17ee3d87f704a5fab854 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,9 +2,31 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.15 .. Yosys 0.15-dev
+Yosys 0.17 .. Yosys 0.17-dev
 --------------------------
 
+Yosys 0.16 .. Yosys 0.17
+--------------------------
+ * New commands and options
+    - Added "write_jny" ( JSON netlist metadata format )
+    - Added "tribuf -formal"
+
+ * SystemVerilog
+    - Fixed automatic `nosync` inference for local variables in `always_comb`
+      procedures not applying to nested blocks and blocks in functions
+
+Yosys 0.15 .. Yosys 0.16
+--------------------------
+ * Various
+    - Added BTOR2 witness file co-simulation.
+    - Simulation calls external vcd2fst for VCD conversion.
+    - Added fst2tb pass - generates testbench for the circuit using
+      the given top-level module and simulus signal from FST file.
+    - yosys-smtbmc: Option to keep going after failed assertions in BMC mode
+
+ * Verific support
+    - Import modules in alphabetic (reproducable) order.
+
 Yosys 0.14 .. Yosys 0.15
 --------------------------