List of major changes and improvements between releases
=======================================================
+Yosys 0.17 .. Yosys 0.17-dev
+--------------------------
+
+Yosys 0.16 .. Yosys 0.17
+--------------------------
+ * New commands and options
+ - Added "write_jny" ( JSON netlist metadata format )
+ - Added "tribuf -formal"
+
+ * SystemVerilog
+ - Fixed automatic `nosync` inference for local variables in `always_comb`
+ procedures not applying to nested blocks and blocks in functions
+
+Yosys 0.15 .. Yosys 0.16
+--------------------------
+ * Various
+ - Added BTOR2 witness file co-simulation.
+ - Simulation calls external vcd2fst for VCD conversion.
+ - Added fst2tb pass - generates testbench for the circuit using
+ the given top-level module and simulus signal from FST file.
+ - yosys-smtbmc: Option to keep going after failed assertions in BMC mode
+
+ * Verific support
+ - Import modules in alphabetic (reproducable) order.
+
+Yosys 0.14 .. Yosys 0.15
+--------------------------
+
+ * Various
+ - clk2fflogic: nice names for autogenerated signals
+ - simulation include support for all flip-flop types.
+ - Added AIGER witness file co-simulation.
+
+ * Verilog
+ - Fixed evaluation of constant functions with variables or arguments with
+ reversed dimensions
+ - Fixed elaboration of dynamic range assignments where the vector is
+ reversed or is not zero-indexed
+ - Added frontend support for time scale delay values (e.g., `#1ns`)
+
+ * SystemVerilog
+ - Added support for accessing whole sub-structures in expressions
+
+ * New commands and options
+ - Added glift command, used to create gate-level information flow tracking
+ (GLIFT) models by the "constructive mapping" approach
+
+ * Verific support
+ - Ability to override default parser mode for verific -f command.
+
+Yosys 0.13 .. Yosys 0.14
+--------------------------
+
+ * Various
+ - Added $bmux and $demux cells and related optimization patterns.
+
+ * New commands and options
+ - Added "bmuxmap" and "dmuxmap" passes
+ - Added "-fst" option to "sim" pass for writing FST files
+ - Added "-r", "-scope", "-start", "-stop", "-at", "-sim", "-sim-gate",
+ "-sim-gold" options to "sim" pass for co-simulation
+
+ * Anlogic support
+ - Added support for BRAMs
+
+Yosys 0.12 .. Yosys 0.13
+--------------------------
+
+ * Various
+ - Use "read" command to parse HDL files from Yosys command-line
+ - Added "yosys -r <topmodule>" command line option
+ - write_verilog: dump zero width sigspecs correctly
+
+ * SystemVerilog
+ - Fixed regression preventing the use array querying functions in case
+ expressions and case item expressions
+ - Fixed static size casts inadvertently limiting the result width of binary
+ operations
+ - Fixed static size casts ignoring expression signedness
+ - Fixed static size casts not extending unbased unsized literals
+ - Added automatic `nosync` inference for local variables in `always_comb`
+ procedures which are always assigned before they are used to avoid errant
+ latch inference
+
+ * New commands and options
+ - Added "clean_zerowidth" pass
+
+ * Verific support
+ - Add YOSYS to the implicitly defined verilog macros in verific
+
+Yosys 0.11 .. Yosys 0.12
+--------------------------
+
+ * Various
+ - Added iopadmap native support for negative-polarity output enable
+ - ABC update
+
+ * SystemVerilog
+ - Support parameters using struct as a wiretype
+
+ * New commands and options
+ - Added "-genlib" option to "abc" pass
+ - Added "sta" very crude static timing analysis pass
+
+ * Verific support
+ - Fixed memory block size in import
+
+ * New back-ends
+ - Added support for GateMate FPGA from Cologne Chip AG
+
+ * Intel ALM support
+ - Added preliminary Arria V support
+
+
+Yosys 0.10 .. Yosys 0.11
+--------------------------
+
+ * Various
+ - Added $aldff and $aldffe (flip-flops with async load) cells
+
+ * SystemVerilog
+ - Fixed an issue which prevented writing directly to a memory word via a
+ connection to an output port
+ - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
+ filling the width of a cell input
+ - Fixed an issue where connecting a slice covering the entirety of a signed
+ signal to a cell input would cause a failed assertion
+
+ * Verific support
+ - Importer support for {PRIM,WIDE_OPER}_DFF
+ - Importer support for PRIM_BUFIF1
+ - Option to use Verific without VHDL support
+ - Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
+ - Added -cfg option for getting/setting Verific runtime flags
-Yosys 0.9 .. Yosys 0.9-dev
+Yosys 0.9 .. Yosys 0.10
--------------------------
* Various
- Added "portlist" command
- Added "check -mapped"
- Added "check -allow-tbuf"
- - Added "autoname" pass
+ - Added "autoname" pass
- Added "write_verilog -extmem"
- Added "opt_mem" pass
- Added "scratchpad" pass
- Added support for parsing the 'bind' construct
- support declaration in procedural for initialization
- support declaration in generate for initialization
+ - Support wand and wor of data types
* Verific support
- Added "verific -L"
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