[> Issues resolved
------------------
- Fix flush_cpu_icache on VexRiscv.
+ - Fix `.data` section placed in rom (#566)
[> Added Features
------------------
- - JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
- - Add CV32E40P CPU support (ex RI5CY).
- - Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
+ - Properly integrate Minerva CPU.
+ - Add nMigen dependency.
+ - Pluggable CPUs.
+ - BIOS history, autocomplete.
+ - Improve boards's programmers.
+ - Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
+ - Speedup Memtest using an LFSR.
+ - Add LedChaser on boards.
- Improve WishboneBridge.
- Improve Diamond constraints.
- - Add LedChaser on boards.
- - Speedup Memtest using an LFSR.
- - Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
- - Improve boards's programmers.
- - BIOS history, autocomplete.
- - Pluggable CPUs.
- - Add nMigen dependency.
- - Properly integrate Minerva CPU.
+ - Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
+ - Add CV32E40P CPU support (ex RI5CY).
+ - JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
+ - Add Symbiflow experimental support on Arty.
+ - Add SDCard (SPI and SD modes) boot from FAT/exFAT filesystems with FatFs.
+ - Simplify boot with boot.json configuration file.
+ - Revert to a single crt0 (avoid ctr/xip variants).
+ - Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
+ - Add AXI-Lite bus standard support.
+ - Add VexRiscv SMP CPU support.
[> API changes/Deprecation
--------------------------
- Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
- Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
- Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
+ - Rename --gateware-toolchain target parameter to --toolchain.
+ - Integrate Zynq's PS7 as a regular CPU (zynq7000) and deprecate SoCZynq.
[> 2020.04, released April 28th, 2020
-------------------------------------