soc/integration/csr_bridge: use registered version only when SDRAM is present.

[litex.git] / CHANGES

diff --git a/CHANGES b/CHANGES
index 397e31fd96b4b29c6a1dc1dfbe1061b6d4ebd789..836fead16a5851756323be19f78abe660beec87f 100644 (file)
--- a/CHANGES
+++ b/CHANGES
@@ -4,6 +4,7 @@
        [> Issues resolved
        ------------------
        - Fix flush_cpu_icache on VexRiscv.
+       - Fix `.data` section placed in rom (#566)
 
        [> Added Features
        ------------------
@@ -21,6 +22,12 @@
        - Add CV32E40P CPU support (ex RI5CY).
        - JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
        - Add Symbiflow experimental support on Arty.
+       - Add SDCard (SPI and SD modes) boot from FAT/exFAT filesystems with FatFs.
+       - Simplify boot with boot.json configuration file.
+       - Revert to a single crt0 (avoid ctr/xip variants).
+       - Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
+       - Add AXI-Lite bus standard support.
+       - Add VexRiscv SMP CPU support.
 
        [> API changes/Deprecation
        --------------------------
@@ -30,6 +37,7 @@
        - Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
        - Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
        - Rename --gateware-toolchain target parameter to --toolchain.
+       - Integrate Zynq's PS7 as a regular CPU (zynq7000) and deprecate SoCZynq.
 
 [> 2020.04, released April 28th, 2020
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