- Revert to a single crt0 (avoid ctr/xip variants).
- Add otional DMA bus for Cache Coherency on CPU(s) with DMA/Cache Coherency interface.
- Add AXI-Lite bus standard support.
+ - Add VexRiscv SMP CPU support.
[> API changes/Deprecation
--------------------------
- Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
- Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
- Rename --gateware-toolchain target parameter to --toolchain.
+ - Integrate Zynq's PS7 as a regular CPU (zynq7000) and deprecate SoCZynq.
[> 2020.04, released April 28th, 2020
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