update README

[libresoc-litex.git] / Makefile

diff --git a/Makefile b/Makefile
index a56d541363fd1f9cb1f678dbaa961b2e93b28205..18916edcccdf0a7976ff25b59091b4440ac2dd6a 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,12 +1,10 @@
 ls1804k:
-       ./ls180soc.py --build --platform=ls180sram4k --num-srams=2
-       cp build/ls180/gateware/ls180.v .
-       cp build/ls180/gateware/mem.init .
-       cp build/ls180/gateware/mem_1.init .
-       cp build/ls180/gateware/mem_2.init .
-       cp build/ls180/gateware/mem_3.init .
-       cp build/ls180/gateware/mem_4.init .
+       ./ls180soc.py --build --platform=ls180sram4k --num-srams=2 --srams4k
+       cp build/ls180sram4k/gateware/ls180sram4k.v ./ls180.v
+       cp build/ls180sram4k/gateware/mem.init .
+       cp build/ls180sram4k/gateware/mem_1.init .
        cp libresoc/libresoc.v .
+       cp libresoc/SPBlock_512W64B8W.v .
        yosys -p 'read_verilog libresoc.v' \
           -p 'write_ilang libresoc_cvt.il'
        yosys -p 'read_verilog ls180.v' \
@@ -21,12 +19,11 @@ ls180:
        cp build/ls180/gateware/ls180.v .
        cp build/ls180/gateware/mem.init .
        cp build/ls180/gateware/mem_1.init .
-       cp build/ls180/gateware/mem_2.init .
-       cp build/ls180/gateware/mem_3.init .
-       cp build/ls180/gateware/mem_4.init .
        cp libresoc/libresoc.v .
+       cp libresoc/SPBlock_512W64B8W.v .
        yosys -p 'read_verilog libresoc.v' \
              -p 'read_verilog ls180.v' \
+             -p 'proc' \
           -p 'write_verilog ls180_cvt.v'
        yosys -p 'read_verilog ls180.v' \
              -p 'read_verilog SPBlock_512W64B8W.v' \
@@ -45,3 +42,7 @@ versaecp5:
 
 versaecp5load:
        ./versa_ecp5.py --sys-clk-freq=55e6 --load
+
+artya7100t:
+       python3 ./versa_ecp5.py --sys-clk-freq=100e6 --build  --fpga=artya7100t \
+                    --toolchain=symbiflow