ls2: add support for the Nexys Video board

[ls2.git] / Makefile

diff --git a/Makefile b/Makefile
index c60893b1398beebf80874d011636694e522a68a5..c8b48e5baa6b942455982f246d532f82dcac3b8b 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -26,7 +26,9 @@ endif
 
 # Hello world
 MEMORY_SIZE=8192
-RAM_INIT_FILE=hello_world/hello_world.bin
+#RAM_INIT_FILE=hello_world/hello_world.bin
+#RAM_INIT_FILE=../microwatt2/tests/xics/xics.bin
+RAM_INIT_FILE=coldboot/coldboot.bin
 SIM_MAIN_BRAM=false
 
 # Micropython
@@ -39,12 +41,12 @@ SIM_MAIN_BRAM=false
 #SIM_MAIN_BRAM=false
 SIM_BRAM_CHAINBOOT=6291456 # 0x600000
 
-FPGA_TARGET ?= VERILATOR
+FPGA_TARGET ?= verilator
 
 ifeq ($(FPGA_TARGET), verilator)
 RESET_LOW=true
-CLK_INPUT=50000000
-CLK_FREQUENCY=50000000
+CLK_INPUT=100000000
+CLK_FREQUENCY=100000000
 clkgen=fpga/clk_gen_bypass.vhd
 endif
 
@@ -57,9 +59,11 @@ microwatt-verilator: ls2.v \
                      verilator/microwatt-verilator.cpp \
                      verilator/uart-verilator.c
        verilator -O3 -CFLAGS "-DCLK_FREQUENCY=$(CLK_FREQUENCY) -I../verilator" \
+       -DDATA_BUS_WIDTH_8 \
     --assert \
        --top-module top \
     --cc ls2.v \
+    --cc external_core_top.v \
     --exe verilator/microwatt-verilator.cpp verilator/uart-verilator.c \
     -o $@ -I../uart16550/rtl/verilog \
        -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT \
@@ -67,6 +71,7 @@ microwatt-verilator: ls2.v \
            -Wno-COMBDLY  \
            -Wno-CASEINCOMPLETE \
            -Wno-WIDTH \
+           -Wno-TIMESCALEMOD \
         --savable \
         --trace \
        #    --unroll-count 256 \