debugging ls180 litex hell

[libresoc-litex.git] / Makefile

diff --git a/Makefile b/Makefile
index 434bcda34c04791ad4408734af93c45fdd43d12f..da4eeec9072a8f2013efad3257cbdf2e0f167def 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,23 @@
+ls1804k:
+       ./ls180soc.py --build --platform=ls180sram4k --num-srams=2
+       cp build/ls180/gateware/ls180.v .
+       cp build/ls180/gateware/mem.init .
+       cp build/ls180/gateware/mem_1.init .
+       cp build/ls180/gateware/mem_2.init .
+       cp build/ls180/gateware/mem_3.init .
+       cp build/ls180/gateware/mem_4.init .
+       cp libresoc/libresoc.v .
+       yosys -p 'read_verilog libresoc.v' \
+          -p 'write_ilang libresoc_cvt.il'
+       yosys -p 'read_verilog ls180.v' \
+             -p 'read_verilog SPBlock_512W64B8W.v' \
+          -p 'write_ilang ls180_cvt.il'
+       yosys -p 'read_ilang ls180_cvt.il' \
+          -p 'read_ilang libresoc_cvt.il' \
+          -p 'write_ilang ls180.il'
+
 ls180:
-       ./ls180soc.py --build --platform=ls180
+       ./ls180soc.py --build --platform=ls180 --num-srams=2
        cp build/ls180/gateware/ls180.v .
        cp build/ls180/gateware/mem.init .
        cp build/ls180/gateware/mem_1.init .