```
[](https://travis-ci.com/enjoy-digital/litex)
+
+> **Note:** In release 2020.04, LiteX switched to Python modules instead of Git submodules. Existing users will have to reinstall LiteX following the [installation guide](https://github.com/enjoy-digital/litex/wiki/Installation#litex-installation-guide).
+
# Welcome to LiteX!
LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create Cores/SoCs (with or without CPU).
-The common components of a SoC are provided directly: Buses and Streams (Wishbone, AXI, Avalon-ST), Interconnect, Common cores (RAM, ROM, Timer, UART, etc...), CPU wrappers/integration, etc... and SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM, PCIe, Ethernet, SATA, etc...) than can be integrated/simulated/build easily with LiteX. It also provides build backends for open-source and vendors toolchains.
+The common components of a SoC are provided directly: Buses and Streams (Wishbone, AXI, Avalon-ST), Interconnect, Common cores (RAM, ROM, Timer, UART, etc...), CPU wrappers/integration, etc... and SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM, PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX. It also provides build backends for open-source and vendors toolchains.
Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
SoC builder to create/develop/debug FPGA SoCs in Python.
| Name | Build Status | Description |
| ------------------------------------------------------------ | ----------------------------------------------------------------------- | ----------------------------- |
-| [LiteDRAM](http://github.com/enjoy-digital/litedram) | [](https://travis-ci.org/enjoy-digital/litedram) | DRAM |
+| [LiteDRAM](http://github.com/enjoy-digital/litedram) | [](https://travis-ci.com/enjoy-digital/litedram) | DRAM |
| [LiteEth](http://github.com/enjoy-digital/liteeth) | [](https://travis-ci.com/enjoy-digital/liteeth) | Ethernet |
| [LitePCIe](http://github.com/enjoy-digital/litepcie) | [](https://travis-ci.com/enjoy-digital/litepcie) | PCIe |
| [LiteSATA](http://github.com/enjoy-digital/litesata) | [](https://travis-ci.com/enjoy-digital/litesata) | SATA |
Provides platforms and targets for the supported boards. All Migen's platforms can also be used in LiteX. The boards present in the LiteX repository are the official ones that are used for development/CI. More boards are available at: https://github.com/litex-hub/litex-boards
# Quick start guide
-0. Install Python 3.5+ and FPGA vendor's development tools.
-1. Install Migen/LiteX and the LiteX's cores:
-
-On MacOS, make sure you have [HomeBrew](https://brew.sh) installed. Then do, ``brew install wget``.
+1. Install Python 3.6+ and FPGA vendor's development tools and/or [Verilator](http://www.veripool.org/).
+2. Install Migen/LiteX and the LiteX's cores:
```sh
$ wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
```sh
$ ./litex_setup.py update
```
-3. Install a RISC-V toolchain:
-For Linux:
-```sh
-$ wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
-$ tar -xvf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
-$ export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
-```
-MacOS:
+> **Note:** On MacOS, make sure you have [HomeBrew](https://brew.sh) installed. Then do, ``brew install wget``.
+
+> **Note:** On Windows, it's possible you'll have to set `SHELL` environment variable to `SHELL=cmd.exe`.
+
+3. Install a RISC-V toolchain (Only if you want to test/create a SoC with a CPU):
```sh
-$ wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-apple-darwin.tar.gz
-$ tar -xvf riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-apple-darwin.tar.gz
-$ export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-apple-darwin/bin/
+$ ./litex_setup.py gcc
```
+
4. Build the target of your board...:
- Go to litex-boards/litex_boards/xxyy/targets (xxyy being community/official/partner) and execute the target you want to build
-5. ... and/or install [Verilator](http://www.veripool.org/) and test LiteX on your computer
+Go to litex-boards/litex_boards/targets and execute the target you want to build.
-On Fedora:
-```sh
-$ sudo dnf install libevent-devel json-c-devel
-```
-On Ubuntu:
+5. ... and/or install [Verilator](http://www.veripool.org/) and test LiteX directly on your computer without any FPGA board:
+
+On Linux (Ubuntu):
```sh
$ sudo apt install libevent-dev libjson-c-dev verilator
-$ litex_sim
+$ lxsim --cpu-type=vexriscv
```
-On MacOS:
-
+On MacOS:
```sh
$ brew install json-c verilator libevent
$ brew cask install tuntap
-$ litex_sim
+$ lxsim --cpu-type=vexriscv
```
6. Run a terminal program on the board's serial port at 115200 8-N-1.
projects / litex.git / blobdiff