remove whitespace

[soc.git] / TLB / test / test_cam_entry.py

diff --git a/TLB/test/test_cam_entry.py b/TLB/test/test_cam_entry.py
index 9fcc6609ab4f29b6270a9d2bac43d7196b8fd362..1ed48f50a8368cc7126fb4e30da5f1ee3ba1f2f0 100644 (file)
--- a/TLB/test/test_cam_entry.py
+++ b/TLB/test/test_cam_entry.py
@@ -6,13 +6,13 @@ from nmigen.compat.sim import run_simulation
 
 from test_helper import assert_eq, assert_ne
 from CamEntry import CamEntry
- 
+
 # This function allows for the easy setting of values to the Cam Entry
 # unless the key is incorrect
 # Arguments:
 #   dut: The CamEntry being tested
 #   c (command): NA (0), Read (1), Write (2), Reserve (3)
-#   d (data): The data to be set  
+#   d (data): The data to be set
 def set_cam_entry(dut, c, d):
     # Write desired values
     yield dut.command.eq(c)
@@ -20,9 +20,9 @@ def set_cam_entry(dut, c, d):
     yield
     # Reset all lines
     yield dut.command.eq(0)
-    yield dut.data_in.eq(0)    
-    yield    
-   
+    yield dut.data_in.eq(0)
+    yield
+
 # Checks the data state of the CAM entry
 # Arguments:
 #   dut: The CamEntry being tested
@@ -33,20 +33,20 @@ def check_data(dut, d, op):
     if op == 0:
         assert_eq("Data", out_d, d)
     else:
-        assert_ne("Data", out_d, d)  
-  
+        assert_ne("Data", out_d, d)
+
 # Checks the match state of the CAM entry
 # Arguments:
 #   dut: The CamEntry being tested
-#   m (Match): The expected match  
+#   m (Match): The expected match
 #   op (Operation): (0 => ==), (1 => !=)
 def check_match(dut, m, op):
     out_m = yield dut.match
     if op == 0:
         assert_eq("Match", out_m, m)
     else:
-        assert_ne("Match", out_m, m)  
-  
+        assert_ne("Match", out_m, m)
+
 # Checks the state of the CAM entry
 # Arguments:
 #   dut: The CamEntry being tested
@@ -57,7 +57,7 @@ def check_match(dut, m, op):
 def check_all(dut, d, m, d_op, m_op):
     yield from check_data(dut, d, d_op)
     yield from check_match(dut, m, m_op)
-    
+
 # This testbench goes through the paces of testing the CamEntry module
 # It is done by writing and then reading various combinations of key/data pairs
 # and reading the results with varying keys to verify the resulting stored
@@ -69,46 +69,46 @@ def testbench(dut):
     match = 0
     yield from set_cam_entry(dut, command, data)
     yield from check_all(dut, data, match, 0, 0)
-    
+
     # Check read miss
     command = 1
     data = 2
     match = 0
     yield from set_cam_entry(dut, command, data)
-    yield from check_all(dut, data, match, 1, 0) 
-    
+    yield from check_all(dut, data, match, 1, 0)
+
     # Check read hit
     command = 1
     data = 1
     match = 1
     yield from set_cam_entry(dut, command, data)
-    yield from check_all(dut, data, match, 0, 0) 
-    
+    yield from check_all(dut, data, match, 0, 0)
+
     # Check overwrite
     command = 2
     data = 5
     match = 0
     yield from set_cam_entry(dut, command, data)
     yield
-    yield from check_all(dut, data, match, 0, 0) 
-    
+    yield from check_all(dut, data, match, 0, 0)
+
     # Check read hit
     command = 1
     data = 5
     match = 1
     yield from set_cam_entry(dut, command, data)
-    yield from check_all(dut, data, match, 0, 0) 
-    
+    yield from check_all(dut, data, match, 0, 0)
+
     # Check reset
     command = 3
     data = 0
     match = 0
     yield from set_cam_entry(dut, command, data)
-    yield from check_all(dut, data, match, 0, 0)     
-    
+    yield from check_all(dut, data, match, 0, 0)
+
     # Extra clock cycle for waveform
     yield
-    
+
 if __name__ == "__main__":
     dut = CamEntry(4)
     run_simulation(dut, testbench(dut), vcd_name="Waveforms/cam_entry_test.vcd")