Add _hard_float check in crt.S.

[riscv-tests.git] / benchmarks / common / crt.S

diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
index 19ff3b262f065873ed20bdd51d95b998f53509cd..bd27f6f330235813f51241fdad9e38b85df06905 100644 (file)
--- a/benchmarks/common/crt.S
+++ b/benchmarks/common/crt.S
@@ -67,8 +67,13 @@ _start:
   li t0, MSTATUS_FS;   csrs mstatus, t0    # enable FPU
   li t0, MSTATUS_XS;   csrs mstatus, t0    # enable accelerator
 
-#ifndef __riscv64
-  li t0, MSTATUS_UA;   csrc mstatus, t0    # disable RV64 for user mode
+#ifdef __riscv64
+  csrr t0, mcpuid
+  # make sure processor supports RV64 if this was compiled for RV64
+  bltz t0, 1f
+  li a0, 1234
+  j tohost_exit
+1:
 #endif
 
   csrr t0, mstatus
@@ -81,6 +86,7 @@ _start:
   and t1, t0, t1
   beqz t1, 1f
 
+#ifdef __riscv_hard_float
   fssr    x0
   fmv.s.x f0, x0
   fmv.s.x f1, x0
@@ -114,13 +120,18 @@ _start:
   fmv.s.x f29,x0
   fmv.s.x f30,x0
   fmv.s.x f31,x0
+#endif
+
 1:
 
+  # initialize global pointer
+  la gp, _gp
+
   la  tp, _end + 63
   and tp, tp, -64
 
   # get core id
-  csrr a0, hartid
+  csrr a0, mhartid
   # for now, assume only 1 core
   li a1, 1
 1:bgeu a0, a1, 1b