Add _hard_float check in crt.S.

[riscv-tests.git] / benchmarks / common / crt.S

diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
index 24e35804867a16a75b7b106feac44e734e88e04a..bd27f6f330235813f51241fdad9e38b85df06905 100644 (file)
--- a/benchmarks/common/crt.S
+++ b/benchmarks/common/crt.S
@@ -1,3 +1,5 @@
+# See LICENSE for license details.
+
 #include "encoding.h"
 
 #ifdef __riscv64
@@ -9,8 +11,24 @@
 #endif
 
   .text
-  .globl _start
+  .align 6
+user_trap_entry:
+  j trap_entry
+
+  .align 6
+supervisor_trap_entry:
+  j supervisor_trap_entry
+
+  .align 6
+hypervisor_trap_entry:
+  j hypervisor_trap_entry
 
+  .align 6
+machine_trap_entry:
+  j trap_entry
+
+  .align 6
+  .globl _start
 _start:
   li  x1, 0
   li  x2, 0
@@ -44,23 +62,31 @@ _start:
   li  x30,0
   li  x31,0
 
-  # initialize status, enable fp, accelerator, interrupts
-  li a0, SR_S | SR_PEI | SR_EF | SR_EA
-  csrw status, a0
+  li t0, MSTATUS_PRV1; csrc mstatus, t0    # run tests in user mode
+  li t0, MSTATUS_IE1;  csrs mstatus, t0    # enable interrupts in user mode
+  li t0, MSTATUS_FS;   csrs mstatus, t0    # enable FPU
+  li t0, MSTATUS_XS;   csrs mstatus, t0    # enable accelerator
 
 #ifdef __riscv64
-  li a0, SR_U64 | SR_S64
-  csrs status, a0
+  csrr t0, mcpuid
+  # make sure processor supports RV64 if this was compiled for RV64
+  bltz t0, 1f
+  li a0, 1234
+  j tohost_exit
+1:
 #endif
 
-  csrr t0, status
-  and t1, t0, SR_EA
+  csrr t0, mstatus
+  li t1, MSTATUS_XS
+  and t1, t0, t1
   sw t1, have_vec, t2
 
   ## if that didn't stick, we don't have a FPU, so don't initialize it
-  and t1, t0, SR_EF
+  li t1, MSTATUS_FS
+  and t1, t0, t1
   beqz t1, 1f
 
+#ifdef __riscv_hard_float
   fssr    x0
   fmv.s.x f0, x0
   fmv.s.x f1, x0
@@ -94,17 +120,21 @@ _start:
   fmv.s.x f29,x0
   fmv.s.x f30,x0
   fmv.s.x f31,x0
+#endif
+
 1:
 
-  la t0, trap_entry
-  csrw evec, t0
+  # initialize global pointer
+  la gp, _gp
 
   la  tp, _end + 63
   and tp, tp, -64
 
-  # get core id and number of cores
-  csrr a0, hartid
-  lw a1, 4(zero)
+  # get core id
+  csrr a0, mhartid
+  # for now, assume only 1 core
+  li a1, 1
+1:bgeu a0, a1, 1b
 
   # give each core 128KB of stack + TLS
 #define STKSHIFT 17
@@ -114,27 +144,12 @@ _start:
   sll sp, sp, STKSHIFT
   add sp, sp, tp
 
-  # offset thread pointer by thread pointer bias
-  lui t0, %tprel_hi(tls_start)
-  add t0, t0, tp, %tprel_add(tls_start)
-  add t0, t0, %tprel_lo(tls_start)
-  sub t0, t0, tp
-  sub tp, tp, t0
-
   la t0, _init
-  csrw epc, t0
-  sret
+  csrw mepc, t0
+  eret
 
 trap_entry:
-  csrw sup0, sp
-  csrw sup1, t0
-  csrr t0, status
-  andi t0, t0, SR_PS
-  bnez t0, 1f
-  la sp, kstacktop
-1:
   addi sp, sp, -272
-  csrr t0, sup1
 
   SREG x1, 8(sp)
   SREG x2, 16(sp)
@@ -168,21 +183,11 @@ trap_entry:
   SREG x30, 240(sp)
   SREG x31, 248(sp)
 
-  csrr t0, sup0
-  csrr t1, status
-  SREG t0, 256(sp)
-  SREG t1, 264(sp)
-
-  csrr a0, cause
-  csrr a1, epc
+  csrr a0, mcause
+  csrr a1, mepc
   mv a2, sp
   jal handle_trap
-  csrw epc, v0
-
-  LREG t0, 256(sp)
-  LREG t1, 264(sp)
-  csrw sup0, t0
-  csrw status, t1
+  csrw mepc, a0
 
   LREG x1, 8(sp)
   LREG x2, 16(sp)
@@ -216,13 +221,17 @@ trap_entry:
   LREG x30, 240(sp)
   LREG x31, 248(sp)
 
-  csrr sp, sup0
-  sret
+  addi sp, sp, 272
+  eret
+
+.section ".tdata.begin"
+.globl _tdata_begin
+_tdata_begin:
 
-.bss
-.align 4
-.skip 4096
-kstacktop:
+.section ".tdata.end"
+.globl _tdata_end
+_tdata_end:
 
-.section .tbss
-tls_start:
+.section ".tbss.end"
+.globl _tbss_end
+_tbss_end: