Enable interrupts in bmarks

[riscv-tests.git] / benchmarks / common / crt.S

diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
index b273900e880957ee7a82f9790c369cd22fc13ca3..e35608e0d56c50fa435e7b1ebf0c504985f7582e 100644 (file)
--- a/benchmarks/common/crt.S
+++ b/benchmarks/common/crt.S
@@ -8,14 +8,6 @@
 # define SREG sw
 #endif
 
-  .data
-  .globl _heapend
-  .globl environ
-_heapend:
-  .word 0
-environ:
-  .word 0
-
   .text
   .globl _start
 
@@ -52,20 +44,22 @@ _start:
   li  x30,0
   li  x31,0
 
+  # initialize status, enable fp, accelerator, interrupts
+  li a0, SR_S | SR_PEI | SR_EF | SR_EA
+  csrw status, a0
+
 #ifdef __riscv64
   li a0, SR_U64 | SR_S64
   csrs status, a0
 #endif
-  csrc status, SR_PS
 
-  # enable fp and accelerator
-  li a0, SR_EF | SR_EA
-  csrs status, a0
-
-  ## if that didn't stick, we don't have an FPU, so don't initialize it
   csrr t0, status
-  and t0, t0, SR_EF
-  beqz t0, 1f
+  and t1, t0, SR_EA
+  sw t1, have_vec, t2
+
+  ## if that didn't stick, we don't have a FPU, so don't initialize it
+  and t1, t0, SR_EF
+  beqz t1, 1f
 
   fssr    x0
   fmv.s.x f0, x0