platforms: fixup to new package names

[freedom-sifive.git] / common.mk

diff --git a/common.mk b/common.mk
index db054830983f75d75ac16e9d71a01f60ad20a8ca..1a1407a7d98681bd41ed4464f0dfb1922309cfa8 100644 (file)
--- a/common.mk
+++ b/common.mk
@@ -46,7 +46,7 @@ $(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.sc
 firrtl := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).fir
 $(firrtl): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR)
        mkdir -p $(dir $@)
-       $(SBT) "run-main freechips.rocketchip.system.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
+       $(SBT) "runMain freechips.rocketchip.system.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
 
 .PHONY: firrtl
 firrtl: $(firrtl)
@@ -72,11 +72,26 @@ endif
 .PHONY: romgen
 romgen: $(romgen)
 
+f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F
+$(f):
+       echo $(VSRCS) > $@
+
+bit := $(BUILD_DIR)/obj/$(MODEL).bit
+$(bit): $(romgen) $(f)
+       cd $(BUILD_DIR); vivado \
+               -nojournal -mode batch \
+               -source $(fpga_common_script_dir)/vivado.tcl \
+               -tclargs \
+               -top-module "$(MODEL)" \
+               -F "$(f)" \
+               -ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \
+               -board "$(BOARD)"
+
+
 # Build .mcs
-mcs := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).mcs
-$(mcs): $(romgen)
-       VSRCS="$(VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
-       cp $(BUILD_DIR)/$(MODEL)/obj/system.mcs $@
+mcs := $(BUILD_DIR)/obj/$(MODEL).mcs
+$(mcs): $(bit)
+       cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
 
 .PHONY: mcs
 mcs: $(mcs)