\frame{
\begin{center}
- \huge{The Libre-SOC Hybrid 3D CPU}\\
- \vspace{32pt}
- \Large{Data-Dependent-Fail-First}\\
+ \huge{Libre-SOC Simple-V Specification \\
+ Advanced features}\\
+ \vspace{24pt}
+ \Large{Data-Dependent Fail-First}\\
\vspace{24pt}
\Large{FOSDEM2024}\\
\vspace{16pt}
- \large{Sponsored by NLnet's PET Programme}\\
+ \large{Funded by NLnet NGI-ASSURE \\
+ EU grant agreement No 957073}\\
\vspace{6pt}
\large{\today}
\end{center}
}
-
-
\begin{frame}[fragile]
\frametitle{Simple-V CMPI in a nutshell}
identical to general-purpose Simple-V DD-FFirst...
\end{itemize}
-}Po
-
-\frame{\frametitle{maxloc}
- \begin{itemize}
- \item "TODO
- \end{itemize}
}
\frame{\frametitle{Pospopcount}
}
-\frame{\frametitle{Pospopcount.s}
+\frame{\frametitle{pospopcount assembler}
\lstinputlisting[language={}]{pospopcount.s}
}
-
\frame{\frametitle{strncpy}
\lstinputlisting[language={}]{strncpy.c}
\begin{itemize}
- \item "TODO
+ \item two simple-looking for-loops,
+ data-dependent in the first.
+ \item sv.cmpi stops at the first zero, /vli includes the zero
+ in VL.
+ \item note the post-increment Load/Store: saves
+ pre-decrementing
+ \item a Vector of CRs is produced which then get tested
+ by the sv.bc/all instruction, counting down CTR
+ per item tested.
+ \item Power ISA added hard-coded data-dependent capacity
+ into vstribr, where SVP64 it is generic (applies
+ to any instruction)
+ \item even the null-ing part is not straightforward as
+ it could be mis-aligned compared to the VSX width.
+ \item end-result: assembler-optimised strncpy on Power
+ ISA v3.0 is a whopping 240 instructions. SVP64 is 10
+ and parallel in HW
\end{itemize}
}
\frame{\frametitle{linked-list walking}
- \begin{center}
- \includegraphics[width=0.6\textwidth]{linked_list_dd.png}
- \end{center}
-
\begin{itemize}
\item "TODO
\end{itemize}
}
-\frame{\frametitle{Summary}
-
- \begin{itemize}
- \item Goal is to create a mass-volume low-power embedded SoC suitable
- for use in netbooks, chromebooks, tablets, smartphones, IoT SBCs.
- \item No way we could implement a project of this magnitude without
- nmigen (being able to use python OO to HDL)
- \item Collaboration with OpenPOWER Foundation and Members absolutely
- essential. No short-cuts. Standards to be developed and ratified
- so that everyone benefits.
- \item Riding the wave of huge stability of OpenPOWER ecosystem
- \item Greatly simplified open 3D and Video drivers reduces product
- development costs for customers
- \item It also happens to be fascinating, deeply rewarding technically
- challenging, and funded by NLnet
-
- \end{itemize}
+\frame{\frametitle{sv.ld/ff=RC1/vli *17, 8(*16)}
+
+ \begin{center}
+ \includegraphics[width=1.0\textwidth]{linked_list_dd.png}
+ \end{center}
}
-\frame{\frametitle{How can you help?}
+\frame{\frametitle{maxloc}
+ \lstinputlisting[language={}]{maxloc.py}
- \vspace{5pt}
+ \begin{itemize}
+ \item "TODO
+ \end{itemize}
+}
- \begin{itemize}
- \item Start here! https://libre-soc.org \\
- Mailing lists https://lists.libre-soc.org \\
- IRC Freenode libre-soc \\
- etc. etc. (it's a Libre project, go figure) \\
- \vspace{3pt}
- \item Can I get paid? Yes! NLnet funded\\
- See https://libre-soc.org/nlnet/\#faq \\
- \vspace{3pt}
- \item Also profit-sharing in any commercial ventures \\
- \vspace{3pt}
- \item How many opportunities to develop Libre SoCs exist,\\
- and actually get paid for it?
- \vspace{3pt}
- \item I'm not a developer, how can I help?\\
- - Plenty of research needed, artwork, website \\
- - Help find customers and OEMs willing to commit (LOI)
- \end{itemize}
+\frame{\frametitle{maxlocassembler}
+
+ \lstinputlisting[language={}]{maxloc.s}
+
}
+\frame{\frametitle{Summary}
+ \begin{itemize}
+ \item SIMD fundamentally assumes element independence.
+ \item No provision in SIMD ISAs or Architectures for
+ inter-element inter-dependence, let alone sequential
+ inter-dependence.
+ \item Simple-V adds features such as Data-Dependent
+ Fail-First as \textit{general concepts},
+ exploiting Condition Registers (Vectorised)
+ \item Hardware Parallelism is \textit{still possible}
+ by exploiting the standard capabilities of
+ Speculative Execution: produce results, hold
+ off writing, post-analyse and cancel the results
+ that should not be written. Uses \textit{existing}
+ standard OoO Micro-architecture
+ \item Huge simplification of algorithms, huge "compactification"
+ just like Zilog Z80 and Intel 8086, yet still parallel
+ \item compact deep-expressive assembler brings CISC
+ capability but RISC-RISC (Prefix-Suffix). SIMD remains
+ at the \textit{back-end in hardware} where it belongs.
+ Not exposed at the programmer.
+ \end{itemize}
+}
\frame{
\begin{center}
{\Huge The end\vspace{12pt}\\
- Thank you\vspace{12pt}\\
- Questions?\vspace{12pt}
+ Thank you\vspace{12pt}
}
\end{center}
\begin{itemize}
\item Discussion: http://lists.libre-soc.org
- \item Freenode IRC \#libre-soc
+ \item OFTC.net IRC \#libre-soc
\item http://libre-soc.org/
- \item http://nlnet.nl/PET
+ \item https://nlnet.nl/project/Libre-SOC-OpenPOWER-ISA
+\item https://bugs.libre-soc.org/show\_bug.cgi?id=676
+\item https://bugs.libre-soc.org/show\_bug.cgi?id=1244
+\item https://libre-soc.org/openpower/sv/cookbook/fortran\_maxloc
\item https://libre-soc.org/nlnet/\#faq
\end{itemize}
}
projects / libreriscv.git / blobdiff