[sim,pk] reorganized status register

[riscv-isa-sim.git] / configure

diff --git a/configure b/configure
index 82ea6a473ebec06c6eedb430a2d620def56a64da..3efe8e7f0f966aa21f76ba43f6cde713009aa460 100755 (executable)
--- a/configure
+++ b/configure
@@ -637,6 +637,7 @@ enable_stow
 enable_optional_subprojects
 enable_fpu
 enable_64bit
+enable_rvc
 '
       ac_precious_vars='build_alias
 host_alias
@@ -1271,6 +1272,7 @@ Optional Features:
                           Enable all optional subprojects
   --disable-fpu           Disable floating-point
   --disable-64bit         Disable 64-bit mode
+  --disable-rvc           Disable instruction compression
 
 Some influential environment variables:
   CC          C compiler command
@@ -4043,6 +4045,19 @@ if test "x$enable_64bit" != "xno"; then :
 $as_echo "#define RISCV_ENABLE_64BIT /**/" >>confdefs.h
 
 
+fi
+
+# Check whether --enable-rvc was given.
+if test "${enable_rvc+set}" = set; then :
+  enableval=$enable_rvc;
+fi
+
+if test "x$enable_rvc" != "xno"; then :
+
+
+$as_echo "#define RISCV_ENABLE_RVC /**/" >>confdefs.h
+
+
 fi
 
 libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a