core: Allow multiple loadstore instructions to be in flight

[microwatt.git] / control.vhdl

diff --git a/control.vhdl b/control.vhdl
index f14e350cd8f04e02b431282ecd5587d66c158e33..34c35e28b0c8b548aefde29bc9cc0c88cf70ba2c 100644 (file)
--- a/control.vhdl
+++ b/control.vhdl
@@ -7,7 +7,7 @@ use work.common.all;
 entity control is
     generic (
         EX1_BYPASS : boolean := true;
-        PIPELINE_DEPTH : natural := 2
+        PIPELINE_DEPTH : natural := 3
         );
     port (
         clk                 : in std_ulogic;
@@ -239,6 +239,10 @@ begin
         elsif complete_in.valid = '1' then
             v_int.outstanding := r_int.outstanding - 1;
         end if;
+        if r_int.outstanding >= PIPELINE_DEPTH + 1 then
+            valid_tmp := '0';
+            stall_tmp := '1';
+        end if;
 
         if rst = '1' then
             v_int := reg_internal_init;