loadstore1/dcache: Send store data one cycle later

[microwatt.git] / dcache.vhdl

diff --git a/dcache.vhdl b/dcache.vhdl
index 1e58e1f907f69a3e79f0d47ed161593409ef96ec..7da67e1c490e7f718dd4e3894018460af769a849 100644 (file)
--- a/dcache.vhdl
+++ b/dcache.vhdl
@@ -1306,7 +1306,7 @@ begin
                     req.real_addr := ra;
                     -- Force data to 0 for dcbz
                     if r0.req.dcbz = '0' then
-                        req.data := r0.req.data;
+                        req.data := d_in.data;
                     else
                         req.data := (others => '0');
                     end if;