return "".join("%02x" % ord(c) for c in s)
class SimpleRegisterTest(GdbTest):
- def check_reg(self, name):
+ def check_reg(self, name, alias):
a = random.randrange(1<<self.hart.xlen)
b = random.randrange(1<<self.hart.xlen)
self.gdb.p("$%s=0x%x" % (name, a))
+ assertEqual(self.gdb.p("$%s" % alias), a)
self.gdb.stepi()
assertEqual(self.gdb.p("$%s" % name), a)
- self.gdb.p("$%s=0x%x" % (name, b))
+ assertEqual(self.gdb.p("$%s" % alias), a)
+ self.gdb.p("$%s=0x%x" % (alias, b))
+ assertEqual(self.gdb.p("$%s" % name), b)
self.gdb.stepi()
assertEqual(self.gdb.p("$%s" % name), b)
+ assertEqual(self.gdb.p("$%s" % alias), b)
def setup(self):
# 0x13 is nop
class SimpleS0Test(SimpleRegisterTest):
def test(self):
- self.check_reg("s0")
+ self.check_reg("s0", "x8")
class SimpleS1Test(SimpleRegisterTest):
def test(self):
- self.check_reg("s1")
+ self.check_reg("s1", "x9")
class SimpleT0Test(SimpleRegisterTest):
def test(self):
- self.check_reg("t0")
+ self.check_reg("t0", "x5")
class SimpleT1Test(SimpleRegisterTest):
def test(self):
- self.check_reg("t1")
+ self.check_reg("t1", "x6")
class SimpleF18Test(SimpleRegisterTest):
- def check_reg(self, name):
+ def check_reg(self, name, alias):
self.gdb.p_raw("$mstatus=$mstatus | 0x00006000")
self.gdb.stepi()
a = random.random()
b = random.random()
self.gdb.p_raw("$%s=%f" % (name, a))
+ assertLess(abs(float(self.gdb.p_raw("$%s" % alias)) - a), .001)
self.gdb.stepi()
assertLess(abs(float(self.gdb.p_raw("$%s" % name)) - a), .001)
- self.gdb.p_raw("$%s=%f" % (name, b))
+ assertLess(abs(float(self.gdb.p_raw("$%s" % alias)) - a), .001)
+ self.gdb.p_raw("$%s=%f" % (alias, b))
+ assertLess(abs(float(self.gdb.p_raw("$%s" % name)) - b), .001)
self.gdb.stepi()
assertLess(abs(float(self.gdb.p_raw("$%s" % name)) - b), .001)
+ assertLess(abs(float(self.gdb.p_raw("$%s" % alias)) - b), .001)
def early_applicable(self):
return self.hart.extensionSupported('F')
def test(self):
- self.check_reg("f18")
+ self.check_reg("f18", "fs2")
class SimpleMemoryTest(GdbTest):
def access_test(self, size, data_type):
self.gdb.command("dump ihex memory %s 0x%x 0x%x" % (b.name,
self.hart.ram, self.hart.ram + self.length))
self.gdb.command("shell cat %s" % b.name)
- for line in b:
+ for line in b.xreadlines():
record_type, address, line_data = ihex_parse(line)
if record_type == 0:
written_data = data[address:address+len(line_data)]
self.gdb.p("interrupt_count")
self.gdb.p("local")
-# Fails nondeterministically.
-#class MulticoreRegTest(GdbTest):
-# compile_args = ("programs/infinite_loop.S", "-DMULTICORE")
-#
-# def early_applicable(self):
-# return len(self.target.harts) > 1
-#
-# def setup(self):
-# self.gdb.load()
-# for hart in self.target.harts:
-# self.gdb.select_hart(hart)
-# self.gdb.p("$pc=_start")
-#
-# def test(self):
-# # Run to main
-# # Hart 0 is the first to be resumed, so we have to set the breakpoint
-# # there. gdb won't actually set the breakpoint until we tell it to
-# # resume.
-# self.gdb.select_hart(self.target.harts[0])
-# self.gdb.b("main")
-# self.gdb.c_all()
-# for hart in self.target.harts:
-# self.gdb.select_hart(hart)
-# assertIn("main", self.gdb.where())
-# self.gdb.select_hart(self.target.harts[0])
-# self.gdb.command("delete breakpoints")
-#
-# # Run through the entire loop.
-# self.gdb.b("main_end")
-# self.gdb.c_all()
-#
-# hart_ids = []
-# for hart in self.target.harts:
-# self.gdb.select_hart(hart)
-# assertIn("main_end", self.gdb.where())
-# # Check register values.
-# hart_id = self.gdb.p("$x1")
-# assertNotIn(hart_id, hart_ids)
-# hart_ids.append(hart_id)
-# for n in range(2, 32):
-# value = self.gdb.p("$x%d" % n)
-# assertEqual(value, hart_ids[-1] + n - 1)
-#
-# # Confirmed that we read different register values for different harts.
-# # Write a new value to x1, and run through the add sequence again.
-#
-# for hart in self.target.harts:
-# self.gdb.select_hart(hart)
-# self.gdb.p("$x1=0x%x" % (hart.index * 0x800))
-# self.gdb.p("$pc=main_post_csrr")
-# self.gdb.c_all()
-# for hart in self.target.harts:
-# self.gdb.select_hart(hart)
-# assertIn("main", self.gdb.where())
-# # Check register values.
-# for n in range(1, 32):
-# value = self.gdb.p("$x%d" % n)
-# assertEqual(value, hart.index * 0x800 + n - 1)
+class MulticoreRegTest(GdbTest):
+ compile_args = ("programs/infinite_loop.S", "-DMULTICORE")
+
+ def early_applicable(self):
+ return len(self.target.harts) > 1
+
+ def setup(self):
+ self.gdb.load()
+ for hart in self.target.harts:
+ self.gdb.select_hart(hart)
+ self.gdb.p("$pc=_start")
+
+ def test(self):
+ # Run to main
+ for hart in self.target.harts:
+ self.gdb.select_hart(hart)
+ self.gdb.b("main")
+ self.gdb.c()
+ assertIn("main", self.gdb.where())
+ self.gdb.command("delete breakpoints")
+
+ # Run through the entire loop.
+ for hart in self.target.harts:
+ self.gdb.select_hart(hart)
+ self.gdb.b("main_end")
+ self.gdb.c()
+ assertIn("main_end", self.gdb.where())
+
+ hart_ids = []
+ for hart in self.target.harts:
+ self.gdb.select_hart(hart)
+ # Check register values.
+ hart_id = self.gdb.p("$x1")
+ assertNotIn(hart_id, hart_ids)
+ hart_ids.append(hart_id)
+ for n in range(2, 32):
+ value = self.gdb.p("$x%d" % n)
+ assertEqual(value, hart_ids[-1] + n - 1)
+
+ # Confirmed that we read different register values for different harts.
+ # Write a new value to x1, and run through the add sequence again.
+
+ for hart in self.target.harts:
+ self.gdb.select_hart(hart)
+ self.gdb.p("$x1=0x%x" % (hart.index * 0x800))
+ self.gdb.p("$pc=main_post_csrr")
+ self.gdb.c()
+ for hart in self.target.harts:
+ self.gdb.select_hart(hart)
+ assertIn("main", self.gdb.where())
+ # Check register values.
+ for n in range(1, 32):
+ value = self.gdb.p("$x%d" % n)
+ assertEqual(value, hart.index * 0x800 + n - 1)
class MulticoreRunHaltStepiTest(GdbTest):
compile_args = ("programs/multicore.c", "-DMULTICORE")
class PrivRw(PrivTest):
def test(self):
"""Test reading/writing priv."""
+ # Leave the PC at _start, where the first 4 instructions should be
+ # legal in any mode.
for privilege in range(4):
self.gdb.p("$priv=%d" % privilege)
self.gdb.stepi()
parsed = parser.parse_args()
target = targets.target(parsed)
+ testlib.print_log_names = parsed.print_log_names
+
if parsed.xlen:
target.xlen = parsed.xlen