Don't clear triggers during execution.

[riscv-tests.git] / debug / programs / entry.S

diff --git a/debug/programs/entry.S b/debug/programs/entry.S
index b507a934a584c99eddabcc3b1128aba34d6c16b5..302d409c55bb3d297c5fc8a1dc5019d27b83f82d 100755 (executable)
--- a/debug/programs/entry.S
+++ b/debug/programs/entry.S
@@ -27,28 +27,43 @@ trap_vector:
   j trap_entry
 
 handle_reset:
-  la t0, trap_entry
+  // If misa doesn't exist (or is following an old spec where it has a
+  // different number), skip the next block.
+  la t0, 3f
   csrw mtvec, t0
   csrwi mstatus, 0
+
+  // make sure these registers exist by seeing if either S or U bits
+  // are set before attempting to zero them out.
+  csrr   t1, misa
+  addi   t2, x0, 1     
+  slli   t2, t2, 20 // U_EXTENSION
+  and    t2, t1, t2
+  bne    x0, t2, 1f
+  addi   t2, x0, 1
+  slli   t2, t2, 18 // S_EXTENSION     
+  and    t2, t1, t2
+  bne    x0, t2, 1f
+  j 2f
+1:
   csrwi mideleg, 0
   csrwi medeleg, 0
+2:
   csrwi mie, 0
+3:
+  la t0, trap_entry
+  csrw mtvec, t0
+  csrwi mstatus, 0
 
   # initialize global pointer
+.option push
+.option norelax
   la gp, __global_pointer$
+.option pop
 
   # initialize stack pointer
   la sp, stack_top
 
-  # Clear all hardware triggers
-  li    t0, ~0
-1:
-  addi  t0, t0, 1
-  csrw  CSR_TSELECT, t0
-  csrw  CSR_TDATA1, zero
-  csrr  t1, CSR_TSELECT
-  beq   t0, t1, 1b
-
   # perform the rest of initialization in C
   j _init